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AgeCommit message (Expand)Author
2020-11-10Bump SNAPSHOT version (#1947)Jack Koenig
2020-11-10Fix SMT Memory Bug (#1942)Kevin Laeufer
2020-11-10Refactor emiter (#1879)Jiuyang Liu
2020-11-09smt: ensure that all signals have a unique name (#1943)Kevin Laeufer
2020-11-07-full64 is required to detect VCS. (#1930)Jiuyang Liu
2020-11-04Remove caching from RenameMap (#1938)Jack Koenig
2020-11-04Add 1.4.x to Mergify (#1920)Jack Koenig
2020-10-27Merge pull request #1932 from freechipsproject/fix_VerilogPrepJiuyang Liu
2020-10-26fix for LoweringCompilersSpec.Jiuyang liu
2020-10-26bug fix for VerilogPrep using wrong type.Jiuyang liu
2020-10-26fix a test not detecting verilog name conflicts.Jiuyang liu
2020-10-13Make {Stage, FirrtlStage}.run protected (#1926)Schuyler Eldridge
2020-10-12Update junit to 4.13.1 (#1925)Scala Steward
2020-10-05Merge pull request #1915 from freechipsproject/fix-negative-literal-fixupJack Koenig
2020-10-01Fix "fix" for negative literals > 32 bitsJack Koenig
2020-09-30Merge pull request #1908 from freechipsproject/fix-direct-mem-to-mem-connsAlbert Magyar
2020-09-30Add test for chaining RW-port rdata as wdata of another memAlbert Magyar
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-30Speed up writing CustomFileEmission with buffering (#1906)Jack Koenig
2020-09-28License reference in maven publishing info (#1907)Chick Markley
2020-09-23Improve Travis Chisel tests (#1903)Jack Koenig
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-09-15Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)Jack Koenig
2020-09-14Hit connect case in DedupModuleTests (#1716)Schuyler Eldridge
2020-09-10Merge pull request #1892 from freechipsproject/chisel-test-branchesAlbert Magyar
2020-09-10Specify appropriate Chisel and Treadle branches for CI testsAlbert Magyar
2020-09-09Make StageOption Unserializable (#1891)Jack Koenig
2020-09-09Loosen inlining restrictions (#1882)Albert Chen
2020-09-06Add --pretty:no-expr-inlining to prevent expression inlining (#1869)Jack Koenig
2020-09-06Support binary files in CustomFileEmission (#1887)Jack Koenig
2020-09-05Better error messages for unserializable annotations (#1885)Jack Koenig
2020-09-04Merge pull request #1883 from freechipsproject/legalize-mem-clocksAlbert Magyar
2020-09-04Add test for mem port clock legalizationAlbert Magyar
2020-09-04Legalize memory port clocksAlbert Magyar
2020-09-01InlineBooleanExpressions: test DontTouch (#1880)Albert Chen
2020-09-01Merge pull request #1877 from freechipsproject/mill_patchJiuyang Liu
2020-09-01reuse CrossSbtModule, make mill compatiable to 2.13.Jiuyang liu
2020-08-31Emitter: add missing parenthesize calls (#1874)Albert Chen
2020-08-28Merge pull request #1875 from freechipsproject/fix-inline-boolsAlbert Magyar
2020-08-28Add test for InlineBooleanExpressions add-not exampleAlbert Magyar
2020-08-28Restrict boolean inlining to avoid context-sensitive width bugsAlbert Magyar
2020-08-28Merge pull request #1876 from freechipsproject/equiv-test-transform-orderAlbert Magyar
2020-08-28Add custom transforms 'upstream' of emitter annotation in equiv testsAlbert Magyar
2020-08-28FlattenSpec: flattening a module with no instaces should be a no-op (#1868)Kevin Laeufer
2020-08-28no re-download jar each time. (#1871)Jiuyang Liu
2020-08-28Deprecate CompilerAnnotation (#1870)Schuyler Eldridge
2020-08-26smt: ignore clock signals when converting to transition system (#1866)Kevin Laeufer
2020-08-26Scalafmt check all (#1867)Kevin Laeufer
2020-08-26Emit parentheses in Verilog for nested unary ops (#1865)Jack Koenig
2020-08-25Inline Boolean Expressions (#1817)Albert Chen
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