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authorJiuyang liu2020-10-26 15:31:49 +0000
committerJiuyang liu2020-10-26 15:31:49 +0000
commit61f3e886affce326a2c09c2f5ba8a69465c0c2ee (patch)
treef396139f5dca9aace34be2cb8e9e1ccfeda1190f
parentb2726dff74847ccebc388b14330dcd54ddcc9895 (diff)
fix for LoweringCompilersSpec.
-rw-r--r--src/test/scala/firrtlTests/LoweringCompilersSpec.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index ffaaf332..54f0af8e 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -249,6 +249,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers {
new firrtl.transforms.FlattenRegUpdate,
firrtl.passes.VerilogModulusCleanup,
new firrtl.transforms.VerilogRename,
+ firrtl.passes.InferTypes,
firrtl.passes.VerilogPrep,
new firrtl.AddDescriptionNodes
)
@@ -273,6 +274,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers {
new firrtl.transforms.DeadCodeElimination,
firrtl.passes.VerilogModulusCleanup,
new firrtl.transforms.VerilogRename,
+ firrtl.passes.InferTypes,
firrtl.passes.VerilogPrep,
new firrtl.AddDescriptionNodes
)