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2021-12-01Merge pull request #2343 from chipsalliance/improve-parserJack Koenig
Improve ANTLR Parser
2021-12-01Use ANTLR Listener to save memory during parsingJack Koenig
The ANTLR-generated concrete syntax tree (CST) takes up much more memory than the parsed .fir file. By using a Listener, we can construct the FIRRTL AST live with CST construction and null out the CST as we consume pieces of it. Not only does this improve performance, it drastically reduces max memory use for the parser.
2021-12-01Handle references better in ANTLR ParserJack Koenig
Tweak the grammar to handle references without left-recursion. Also split references and subreferences out from the regular expression rule to make their parsing more efficient.
2021-12-01Ignore firrtl.antlr package in API doc generationJack Koenig
The classes should not really be part of the firrtl public API to begin with and they cause issues during ScalaDoc generation.
2021-12-01Make formal_equiv.sh robust to changes to ANTLR & ProtobufJack Koenig
2021-11-30[deprecation clean up] remove trait firrtl.util.BackendCompilationUtilities ↵Jiuyang Liu
(#2423) Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-30Update sbt-scalafix to 0.9.33 (#2431)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-29[deprecation clean up] remove firrtl.ExecutionOptionsManager (#2422)Jiuyang Liu
Also remove all related APIs: ComposableOptions HasParser CommonOptions HasCommonOptions FirrtlExecutionOptions HasFirrtlOptions FirrtlExecutionResult FirrtlExecutionSuccess FirrtlExecutionFailure ExecutionOptionsManager firrtl.stage.DriverCompatibility.firrtlResultView logger.Logger.makeScope OutputConfig SingleFile OneFilePerModule * Change default LogLevel to None which means "unset" Logger.getGlobalLevel then returns LogLevel.Warn when the current value is LogLevel.None. This preserves the behavior of the default being "Warn" but now uses LogLevel.None to indicate "I'm not setting the value." This resolves issues where it was not possible to tell if annotations were actually setting the log level or if the default level of warn was just being filled in. Co-authored-by: sinofp <sinofp@tuta.io> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-23Enable memory initialization in synthesis for FPGA targets (#2430)Carlos Eduardo
2021-11-23[deprecation clean up] Remove firrtl.Driver (#2419)Jiuyang Liu
Co-authored-by: sinofp <sinofp@tuta.io>
2021-11-23fix tests that depend on Driver (#2429)Jiuyang Liu
Co-authored-by: sinofp <sinofp@tuta.io>
2021-11-22remove firrtl.transforms.BlackBoxSourceHelper.fileListName. (#2426)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-22remove firrtl.transforms.InferResets.DifferingDriverTypesException (#2425)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-22remove firrtl.transforms.InlineAcrossCastsTransform. (#2424)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-22remove firrtl.FIRRTLException (#2421)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-22[deprecation clean up] remove deprecated API in firrtl.Utils (#2420)Jiuyang Liu
* remove firrtl.Utils.get_flip. * remove firrtl.Utils.indent.
2021-11-20Update sbt-ci-release to 1.5.10 (#2418)Scala Steward
2021-11-20Update scalacheck-1-14, ... to 3.2.1.0 (#1850)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-20Update sbt-ci-release to 1.5.9 (#2364)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-20Update scala-parallel-collections to 1.0.4 (#2377)Scala Steward
* Update scala-parallel-collections to 1.0.4 * Update scala-parallel-collections to 1.0.4 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-20Update sbt-mima-plugin to 1.0.1 (#2385)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-20Update sbt-protobuf to 0.7.1 (#2378)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-20Update sbt-scalafix to 0.9.32 (#2414)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-20Update sbt-scalafmt to 2.4.4 (#2417)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-20Update commons-text to 1.9 (#1789)Scala Steward
2021-11-20Update sbt-assembly to 1.1.0 (#1706)Scala Steward
2021-11-20Update scala-library, scala-reflect to 2.12.15 (#2358)Scala Steward
2021-11-20Update scala-library, scala-reflect to 2.13.7 (#2401)Scala Steward
* Update sbt-scalafix to 0.9.32 * Update scala-library, scala-reflect to 2.13.7
2021-11-19Disable random init (#2396)Jiuyang Liu
* Add option to disable random mem/reg init Co-authored-by: Jiuyang Liu <liu@jiuyang.me> * fix for code review. Co-authored-by: SharzyL <me@sharzy.in>
2021-11-12Let firrtl based applications run despite loading unknown annotations (#2387)Chick Markley
An application like barstools may contain a main that loads an annotations file containing annotation classes that are not on it's classpath. This change allows unknown annotations to be preserved by wrapping them in a UnrecognizedAnnotation. If annotations are then output to a file, they will be unwrapped during serialization This feature can be enabled via an AllowUnrecognizedAnnotations annotation Co-authored-by: chick <chick.markley@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-12Update spec on extmodule with defname, parameter (#2413)Schuyler Eldridge
Add defname, parameter to extmodule spec, NFC Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-11-11Update sbt-unidoc to 0.5.0 (#2394)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-11Update json4s-native to 3.6.12 (#2406)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-11Update sbt-scoverage to 1.9.2 (#2402)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-11Update antlr4, antlr4-runtime to 4.9.3 (#2407)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-10ci: use official action to install oss cad tools (#2412)Kevin Laeufer
2021-11-10smt: fix handling of div primitive in formal backend (#2409)Kevin Laeufer
We never tested the case where the width of the numerator was less than the denominator. This should fix any issue with this combination.
2021-11-04BlackBoxSourceHelper: ensure trailing newline in .f file (#2405)Kevin Laeufer
2021-10-28typo: correct Error Info (#2398)SingularityKChen
+ correct the Error Info of "At least one dedupable annotation..."
2021-10-19Remove The WriteEmitted Phase (#2390)David Biancolin
2021-10-18Favor os-lib write.over in WriteEmitted (#2389)David Biancolin
2021-10-09Support parsing missing keywords as ids (#2381)Jack Koenig
Reset, AsyncReset, Interval, attach, assert, assume, and cover have all been added as keywords but not added to the allowlist for parsing as ids.
2021-10-05Merge pull request #2380 from chipsalliance/dev/seldridge/issue-2379Jack Koenig
Hotfix for Vector Reg Init LegalizeConnects Bug
2021-10-04Add test of #2379 issue, NFCSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-10-04Hotfix for Vector Reg Init LegalizeConnects BugSchuyler Eldridge
Add a private pass, LegalizeConnectsOnly, that behaves like LegalizeConnects, but only pads connects instead of connects and register inits. Padding is necessary for ReplSeqMem, but ReplSeqMem runs before LowerTypes and vector registers can still exist at this point. Connects, conversely, are all blown out by ExpandConnects and can be safely, blindly treated as ground type. Fixes #2379. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-09-29TopWiring: filter out unnamed declarations when building source lists (#2376)David Biancolin
* Demonstrate a couple failing cases * Have TopWiring ignore unnamed declarations as potential sources
2021-09-29Have Flatten & InlineInstances remove their annotations (#2374)David Biancolin
* Have Flatten & InlineInstances remove their annotations * Format
2021-09-29Add RTLIL Backend. (#2331)Nicolas Machado
* Added RTLIL Backend. * Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing. * Fix build on scala 2.13 * Add additional equivalence test, make some bugfixes and perf opts to the emitter. * Final changes as requested by Kevin, code cleanup, add support for formal cells.
2021-09-27ci: switch from container to Tabby OSS CAD Suite (#2365)Kevin Laeufer
2021-09-24spec: Fix formatting of example of memory port types. (#2368)Richard Xia
8abf3085e3efb2b6dd3e123f13577b367d3f2695 reordered the fields, but it unintentionally placed a closing brace before the actual end of the write port type. This moves the brace to the end of the port. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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