diff options
| author | Richard Xia | 2021-09-23 17:24:59 -0700 |
|---|---|---|
| committer | GitHub | 2021-09-24 00:24:59 +0000 |
| commit | b2cae19bb7a3e29fe7311e9a288176610826ed03 (patch) | |
| tree | a588154607265e3d69629b19c3bb117eede40c96 | |
| parent | 034445e31ec53100abe259d407e62e278fdb50fa (diff) | |
spec: Fix formatting of example of memory port types. (#2368)
8abf3085e3efb2b6dd3e123f13577b367d3f2695 reordered the fields, but it
unintentionally placed a closing brace before the actual end of the
write port type. This moves the brace to the end of the port.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
| -rw-r--r-- | spec/spec.pdf | bin | 339566 -> 340133 bytes | |||
| -rw-r--r-- | spec/spec.tex | 4 |
2 files changed, 2 insertions, 2 deletions
diff --git a/spec/spec.pdf b/spec/spec.pdf Binary files differindex 2eaac920..7a3bec8b 100644 --- a/spec/spec.pdf +++ b/spec/spec.pdf diff --git a/spec/spec.tex b/spec/spec.tex index 7d4d8ef2..3a9da4a2 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -902,9 +902,9 @@ In the example above, the type of \verb|mymem| is: flip data: {real:SInt<16>, imag:SInt<16>}} flip w: {addr: UInt<8>, en: UInt<1>, - clk: Clock}, + clk: Clock, data: {real:SInt<16>, imag:SInt<16>}, - mask: {real:UInt<1>, imag:UInt<1>}} + mask: {real:UInt<1>, imag:UInt<1>}}} \end{lstlisting} The following sections describe how a memory's field types are calculated and the behavior of each type of memory port. |