From b2cae19bb7a3e29fe7311e9a288176610826ed03 Mon Sep 17 00:00:00 2001
From: Richard Xia
Date: Thu, 23 Sep 2021 17:24:59 -0700
Subject: spec: Fix formatting of example of memory port types. (#2368)

8abf3085e3efb2b6dd3e123f13577b367d3f2695 reordered the fields, but it
unintentionally placed a closing brace before the actual end of the
write port type. This moves the brace to the end of the port.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 spec/spec.pdf | Bin 339566 -> 340133 bytes
 spec/spec.tex |   4 ++--
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/spec/spec.pdf b/spec/spec.pdf
index 2eaac920..7a3bec8b 100644
Binary files a/spec/spec.pdf and b/spec/spec.pdf differ
diff --git a/spec/spec.tex b/spec/spec.tex
index 7d4d8ef2..3a9da4a2 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -902,9 +902,9 @@ In the example above, the type of \verb|mymem| is:
            flip data: {real:SInt<16>, imag:SInt<16>}}
  flip w: {addr: UInt<8>,
           en: UInt<1>,
-          clk: Clock},
+          clk: Clock,
           data: {real:SInt<16>, imag:SInt<16>},
-          mask: {real:UInt<1>, imag:UInt<1>}}
+          mask: {real:UInt<1>, imag:UInt<1>}}}
 \end{lstlisting}
 
 The following sections describe how a memory's field types are calculated and the behavior of each type of memory port.
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