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AgeCommit message (Expand)Author
2021-05-04Fix SBT deprecation warnings (#2214)Jack Koenig
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
2020-07-13add .bloop and .metals to .gitignore (#1761)Albert Chen
2020-06-09Refactor benchmark_code_compile.py to have job running utilityJack Koenig
2020-04-13Add new test jar to .gitignore (#1520)Albert Magyar
2020-02-13Mill support (#1368)Sequencer
2018-01-15WiringTransform Refactor (#648)Schuyler Eldridge
2017-07-26Flatten transformation (#631)Andrey Ayupov
2017-01-31Replace createTempDirectory with createTestDirectory (#427)Jack Koenig
2016-10-17Add fixed point type (#322)Adam Izraelevitz
2016-02-09WIP. Got to-working-ir workingazidar
2016-01-16Ignore eclipse .projectducky
2016-01-16Default platform-agnostic, ignore platform-specific FileCheckducky
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2015-10-08Install Stanza as a dependency of anything that uses itPalmer Dabbelt
2015-10-02Merged in Scala implementation of FIRRTL IR, parser, and serialization (ie. A...Jack
2015-08-26Added regression testazidar
2015-08-20Updated .gitignoreazidar
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates reaso...azidar
2015-05-02Added a infrastructure for check passes, and wrote a fewazidar
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-08Finished expand whens. started infer widths. added pdf for people to viewazidar
2015-03-04Finished infer-types passazidar
2015-02-24Updated tests, and included a check for the name of the pass, whichazidar
2015-02-20Rewrote the initialize-register pass, now correctly implementedazidar
2015-02-19Added compiler flags to allow tests to select which passes they test.azidar
2015-02-18Added more testing infrastructre, and Makefile to build firrtlazidar
2015-02-18Reimplemented to-working-ir. Changed Command to Stmt. Modified printing of IR...azidar
2015-02-13First commit.azidar
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