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-rw-r--r--test/passes/const-prop/bits.fir2
-rw-r--r--test/passes/const-prop/rsh.fir4
-rw-r--r--test/passes/expand-whens/bundle-init.fir4
-rw-r--r--test/passes/expand-whens/reg-dwc.fir4
-rw-r--r--test/passes/expand-whens/reg-wdc.fir6
-rw-r--r--test/passes/infer-types/bundle.fir2
-rw-r--r--test/passes/infer-types/gcd.fir2
-rw-r--r--test/passes/lower-to-ground/bundle-vecs.fir12
-rw-r--r--test/passes/lower-to-ground/nested-vec.fir8
-rw-r--r--test/passes/remove-accesses/bundle-vecs.fir20
-rw-r--r--test/passes/remove-accesses/simple3.fir4
-rw-r--r--test/passes/remove-accesses/simple4.fir4
-rw-r--r--test/passes/remove-accesses/simple5.fir2
-rw-r--r--test/passes/split-exp/split-in-when.fir2
14 files changed, 38 insertions, 38 deletions
diff --git a/test/passes/const-prop/bits.fir b/test/passes/const-prop/bits.fir
index 78c450a9..74aa19de 100644
--- a/test/passes/const-prop/bits.fir
+++ b/test/passes/const-prop/bits.fir
@@ -1,7 +1,7 @@
; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
;CHECK: Constant Propagation
-;CHECK: node x = UInt("h7")
+;CHECK: node x = UInt<3>("h7")
;CHECK: Finished Constant Propagation
circuit top :
diff --git a/test/passes/const-prop/rsh.fir b/test/passes/const-prop/rsh.fir
index 4159899f..5ed8b1be 100644
--- a/test/passes/const-prop/rsh.fir
+++ b/test/passes/const-prop/rsh.fir
@@ -1,8 +1,8 @@
; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
;CHECK: Constant Propagation
-;CHECK: x <= UInt("h1f")
-;CHECK: y <= SInt("h20")
+;CHECK: x <= UInt<5>("h1f")
+;CHECK: y <= SInt<6>("h20")
;CHECK: Finished Constant Propagation
circuit top :
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index f4ae9f6a..333619d9 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -21,7 +21,7 @@ circuit top :
; CHECK: w.y <= a
; CHECK: r.x <= a
; CHECK: r.y <= b
-; CHECK: a <= UInt("h1")
-; CHECK: b <= UInt("h2")
+; CHECK: a <= UInt<1>("h1")
+; CHECK: b <= UInt<2>("h2")
; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
index e8267861..6713b1f2 100644
--- a/test/passes/expand-whens/reg-dwc.fir
+++ b/test/passes/expand-whens/reg-dwc.fir
@@ -16,8 +16,8 @@ circuit top :
; CHECK: module top :
; CHECK: wire p : UInt
; CHECK: reg r : UInt
-; CHECK: p <= UInt("h1")
-; CHECK: r <= mux(p, UInt("h2"), r)
+; CHECK: p <= UInt<1>("h1")
+; CHECK: r <= mux(p, UInt<2>("h2"), r)
; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
index b19b8bca..6e8e7c04 100644
--- a/test/passes/expand-whens/reg-wdc.fir
+++ b/test/passes/expand-whens/reg-wdc.fir
@@ -17,9 +17,9 @@ circuit top :
; CHECK: wire p : UInt
; CHECK: reg r : UInt<2>, clk with :
; CHECK: reset => (reset, r)
-; CHECK: p <= UInt("h1")
-; CHECK-NOT: r <= mux(p, UInt("h2"), r)
-; CHECK: r <= UInt("h2")
+; CHECK: p <= UInt<1>("h1")
+; CHECK-NOT: r <= mux(p, UInt<2>("h2"), r)
+; CHECK: r <= UInt<2>("h2")
; CHECK: Finished Expand Whens
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index 12cc58b1..0a2d2e4f 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -26,7 +26,7 @@ circuit top :
;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt>
;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt[10]@<t:UInt>>
;CHECK: node b = a@<t:UInt[10]@<t:UInt>>[2]@<t:UInt>
-;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
+;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt<2>("h3")@<t:UInt>]
;CHECK: Finished Infer Types
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index d419ce35..398a4944 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -20,7 +20,7 @@ circuit top :
reg y : UInt,clk with :
reset => (reset,UInt(42))
; CHECK: reg x : UInt, clk@<t:Clock> with :
- ;CHECK:reset => (reset@<t:UInt>, UInt("h0")@<t:UInt>)
+ ;CHECK:reset => (reset@<t:UInt>, UInt<1>("h0")@<t:UInt>)
when gt(x, y) :
;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
inst s of subtracter
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index cf581ab7..d6af7a82 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -25,14 +25,14 @@ circuit top :
; CHECK: wire GEN_3 : UInt<32>
; CHECK: j_x <= GEN_0
; CHECK: j_y <= GEN_3
-; CHECK: a_0_x <= mux(eq(UInt("h0"), i), GEN_2, UInt("h0"))
-; CHECK: a_0_y <= mux(eq(UInt("h0"), i), GEN_1, UInt("h0"))
-; CHECK: a_1_x <= mux(eq(UInt("h1"), i), GEN_2, UInt("h0"))
-; CHECK: a_1_y <= mux(eq(UInt("h1"), i), GEN_1, UInt("h0"))
-; CHECK: GEN_0 <= mux(eq(UInt("h1"), i), a_1_x, a_0_x)
+; CHECK: a_0_x <= mux(eq(UInt<1>("h0"), i), GEN_2, UInt<1>("h0"))
+; CHECK: a_0_y <= mux(eq(UInt<1>("h0"), i), GEN_1, UInt<1>("h0"))
+; CHECK: a_1_x <= mux(eq(UInt<1>("h1"), i), GEN_2, UInt<1>("h0"))
+; CHECK: a_1_y <= mux(eq(UInt<1>("h1"), i), GEN_1, UInt<1>("h0"))
+; CHECK: GEN_0 <= mux(eq(UInt<1>("h1"), i), a_1_x, a_0_x)
; CHECK: GEN_1 <= j_y
; CHECK: GEN_2 <= j_x
-; CHECK: GEN_3 <= mux(eq(UInt("h1"), i), a_1_y, a_0_y)
+; CHECK: GEN_3 <= mux(eq(UInt<1>("h1"), i), a_1_y, a_0_y)
; CHECK: Finished Lower Types
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index fcdee5bc..7f9306ce 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -54,12 +54,12 @@ circuit top :
;CHECK: writer => c
;CHECK: m_x.c.data <= k_x
;CHECK: m_y.c.data <= k_y
-;CHECK: m_x.c.mask <= UInt("h1")
-;CHECK: m_y.c.mask <= UInt("h1")
+;CHECK: m_x.c.mask <= UInt<1>("h1")
+;CHECK: m_y.c.mask <= UInt<1>("h1")
;CHECK: m_x.c.addr <= i
;CHECK: m_y.c.addr <= i
-;CHECK: m_x.c.en <= UInt("h1")
-;CHECK: m_y.c.en <= UInt("h1")
+;CHECK: m_x.c.en <= UInt<1>("h1")
+;CHECK: m_y.c.en <= UInt<1>("h1")
;CHECK: m_x.c.clk <= clk
;CHECK: m_y.c.clk <= clk
diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir
index e618892e..6370ace1 100644
--- a/test/passes/remove-accesses/bundle-vecs.fir
+++ b/test/passes/remove-accesses/bundle-vecs.fir
@@ -20,25 +20,25 @@ circuit top :
b.y <= UInt(1)
; CHECK: wire i : UInt<1>
-; CHECK: i <= UInt("h1")
+; CHECK: i <= UInt<1>("h1")
; CHECK: wire j : UInt<32>
-; CHECK: j <= UInt("h1")
+; CHECK: j <= UInt<1>("h1")
; CHECK: wire a : { x : UInt<32>, flip y : UInt<32>}[2]
-; CHECK: a[0].x <= UInt("h1")
-; CHECK: a[0].y <= UInt("h1")
-; CHECK: a[1].x <= UInt("h1")
-; CHECK: a[1].y <= UInt("h1")
+; CHECK: a[0].x <= UInt<1>("h1")
+; CHECK: a[0].y <= UInt<1>("h1")
+; CHECK: a[1].x <= UInt<1>("h1")
+; CHECK: a[1].y <= UInt<1>("h1")
; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>}
; CHECK: wire GEN_0 : UInt<32>
; CHECK: GEN_0 <= a[0].x
-; CHECK: when eq(UInt("h1"), i) : GEN_0 <= a[1].x
+; CHECK: when eq(UInt<1>("h1"), i) : GEN_0 <= a[1].x
; CHECK: b.x <= GEN_0
; CHECK: wire GEN_1 : UInt<32>
-; CHECK: when eq(UInt("h0"), i) : a[0].y <= GEN_1
-; CHECK: when eq(UInt("h1"), i) : a[1].y <= GEN_1
+; CHECK: when eq(UInt<1>("h0"), i) : a[0].y <= GEN_1
+; CHECK: when eq(UInt<1>("h1"), i) : a[1].y <= GEN_1
; CHECK: GEN_1 <= b.y
; CHECK: j <= b.x
-; CHECK: b.y <= UInt("h1")
+; CHECK: b.y <= UInt<1>("h1")
; CHECK: Finished Remove Access
; CHECK: Done!
diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir
index 6305e0c9..9aa0f34f 100644
--- a/test/passes/remove-accesses/simple3.fir
+++ b/test/passes/remove-accesses/simple3.fir
@@ -13,8 +13,8 @@ circuit top :
a <= in
;CHECK: wire GEN_0 : UInt<32>
-;CHECK: when eq(UInt("h0"), i) : m[0] <= GEN_0
-;CHECK: when eq(UInt("h1"), i) : m[1] <= GEN_0
+;CHECK: when eq(UInt<1>("h0"), i) : m[0] <= GEN_0
+;CHECK: when eq(UInt<1>("h1"), i) : m[1] <= GEN_0
;CHECK: GEN_0 <= a
;CHECK: Finished Remove Accesses
diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir
index 4766214c..f4f3a6a5 100644
--- a/test/passes/remove-accesses/simple4.fir
+++ b/test/passes/remove-accesses/simple4.fir
@@ -12,8 +12,8 @@ circuit top :
m[1].y <= UInt("h1")
m[i].x <= in.x
-;CHECK: when eq(UInt("h0"), i) : m[0].x <= GEN_0
-;CHECK: when eq(UInt("h1"), i) : m[1].x <= GEN_0
+;CHECK: when eq(UInt<1>("h0"), i) : m[0].x <= GEN_0
+;CHECK: when eq(UInt<1>("h1"), i) : m[1].x <= GEN_0
;CHECK: GEN_0 <= in
;CHECK: Finished Remove Accesses
;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir
index d2e31537..e21dcf1a 100644
--- a/test/passes/remove-accesses/simple5.fir
+++ b/test/passes/remove-accesses/simple5.fir
@@ -15,7 +15,7 @@ circuit top :
;CHECK: when i :
;CHECK: GEN_0 <= m[0]
-;CHECK: when eq(UInt("h1"), i) : GEN_0 <= m[1]
+;CHECK: when eq(UInt<1>("h1"), i) : GEN_0 <= m[1]
;CHECK: o <= GEN_0
;CHECK: Finished Remove Accesses
;CHECK: Done!
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
index 207ad757..47caa16b 100644
--- a/test/passes/split-exp/split-in-when.fir
+++ b/test/passes/split-exp/split-in-when.fir
@@ -16,7 +16,7 @@ circuit Top :
;CHECK: node GEN_0 = subw(a, c)
;CHECK: node GEN_1 = bits(GEN_0, 3, 3)
-;CHECK: node GEN_2 = eq(UInt("h0"), UInt("hd"))
+;CHECK: node GEN_2 = eq(UInt<5>("h0"), UInt<4>("hd"))
;CHECK: node GEN_3 = addw(b, c)
;CHECK: node GEN_4 = addw(a, GEN_3)
;CHECK: node GEN_5 = subw(c, b)
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 12:24:13 +0000