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-rw-r--r--test/passes/remove-accesses/bundle-vecs.fir20
-rw-r--r--test/passes/remove-accesses/simple3.fir4
-rw-r--r--test/passes/remove-accesses/simple4.fir4
-rw-r--r--test/passes/remove-accesses/simple5.fir2
4 files changed, 15 insertions, 15 deletions
diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir
index e618892e..6370ace1 100644
--- a/test/passes/remove-accesses/bundle-vecs.fir
+++ b/test/passes/remove-accesses/bundle-vecs.fir
@@ -20,25 +20,25 @@ circuit top :
b.y <= UInt(1)
; CHECK: wire i : UInt<1>
-; CHECK: i <= UInt("h1")
+; CHECK: i <= UInt<1>("h1")
; CHECK: wire j : UInt<32>
-; CHECK: j <= UInt("h1")
+; CHECK: j <= UInt<1>("h1")
; CHECK: wire a : { x : UInt<32>, flip y : UInt<32>}[2]
-; CHECK: a[0].x <= UInt("h1")
-; CHECK: a[0].y <= UInt("h1")
-; CHECK: a[1].x <= UInt("h1")
-; CHECK: a[1].y <= UInt("h1")
+; CHECK: a[0].x <= UInt<1>("h1")
+; CHECK: a[0].y <= UInt<1>("h1")
+; CHECK: a[1].x <= UInt<1>("h1")
+; CHECK: a[1].y <= UInt<1>("h1")
; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>}
; CHECK: wire GEN_0 : UInt<32>
; CHECK: GEN_0 <= a[0].x
-; CHECK: when eq(UInt("h1"), i) : GEN_0 <= a[1].x
+; CHECK: when eq(UInt<1>("h1"), i) : GEN_0 <= a[1].x
; CHECK: b.x <= GEN_0
; CHECK: wire GEN_1 : UInt<32>
-; CHECK: when eq(UInt("h0"), i) : a[0].y <= GEN_1
-; CHECK: when eq(UInt("h1"), i) : a[1].y <= GEN_1
+; CHECK: when eq(UInt<1>("h0"), i) : a[0].y <= GEN_1
+; CHECK: when eq(UInt<1>("h1"), i) : a[1].y <= GEN_1
; CHECK: GEN_1 <= b.y
; CHECK: j <= b.x
-; CHECK: b.y <= UInt("h1")
+; CHECK: b.y <= UInt<1>("h1")
; CHECK: Finished Remove Access
; CHECK: Done!
diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir
index 6305e0c9..9aa0f34f 100644
--- a/test/passes/remove-accesses/simple3.fir
+++ b/test/passes/remove-accesses/simple3.fir
@@ -13,8 +13,8 @@ circuit top :
a <= in
;CHECK: wire GEN_0 : UInt<32>
-;CHECK: when eq(UInt("h0"), i) : m[0] <= GEN_0
-;CHECK: when eq(UInt("h1"), i) : m[1] <= GEN_0
+;CHECK: when eq(UInt<1>("h0"), i) : m[0] <= GEN_0
+;CHECK: when eq(UInt<1>("h1"), i) : m[1] <= GEN_0
;CHECK: GEN_0 <= a
;CHECK: Finished Remove Accesses
diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir
index 4766214c..f4f3a6a5 100644
--- a/test/passes/remove-accesses/simple4.fir
+++ b/test/passes/remove-accesses/simple4.fir
@@ -12,8 +12,8 @@ circuit top :
m[1].y <= UInt("h1")
m[i].x <= in.x
-;CHECK: when eq(UInt("h0"), i) : m[0].x <= GEN_0
-;CHECK: when eq(UInt("h1"), i) : m[1].x <= GEN_0
+;CHECK: when eq(UInt<1>("h0"), i) : m[0].x <= GEN_0
+;CHECK: when eq(UInt<1>("h1"), i) : m[1].x <= GEN_0
;CHECK: GEN_0 <= in
;CHECK: Finished Remove Accesses
;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir
index d2e31537..e21dcf1a 100644
--- a/test/passes/remove-accesses/simple5.fir
+++ b/test/passes/remove-accesses/simple5.fir
@@ -15,7 +15,7 @@ circuit top :
;CHECK: when i :
;CHECK: GEN_0 <= m[0]
-;CHECK: when eq(UInt("h1"), i) : GEN_0 <= m[1]
+;CHECK: when eq(UInt<1>("h1"), i) : GEN_0 <= m[1]
;CHECK: o <= GEN_0
;CHECK: Finished Remove Accesses
;CHECK: Done!