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-rw-r--r--test/passes/expand-whens/scoped-reg.fir6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir
index 20c91386..b71a5d50 100644
--- a/test/passes/expand-whens/scoped-reg.fir
+++ b/test/passes/expand-whens/scoped-reg.fir
@@ -1,12 +1,12 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Expand Whens
circuit top :
- module A :
+ module top :
wire p : UInt
when p :
reg r : UInt
on-reset r := UInt(10)
r := UInt(20)
-; CHECK: r := Register(mux-uu(reset, UInt(10), UInt(20)), mux-uu(reset, UInt(1), p))
+; CHECK: r := Register(mux(reset, UInt(10), UInt(20)), mux(reset, UInt(1), p))
; CHECK: Finished Expand Whens