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; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p c | tee %s.out | FileCheck %s
; CHECK: Expand Whens
circuit top :
module A :
wire p : UInt
when p :
reg r : UInt
on-reset r := UInt(10)
r := UInt(20)
; CHECK: r := Register(mux-uu(reset, UInt(10), UInt(20)), mux-uu(reset, UInt(1), p))
; CHECK: Finished Expand Whens
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