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-rw-r--r--test/parser/gcd.fir44
1 files changed, 23 insertions, 21 deletions
diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir
index fad3b41d..e0958a7a 100644
--- a/test/parser/gcd.fir
+++ b/test/parser/gcd.fir
@@ -9,21 +9,21 @@ circuit GCD :
input a : UInt<16>
input b : UInt<16>
- reg x : UInt<16>,clk,reset
- reg y : UInt<16>,clk,reset
+ reg x : UInt<16>,clk
+ reg y : UInt<16>,clk
node T_17 = gt(x, y)
when T_17 :
- node T_18 = subw(x, y)
- x := T_18
+ node T_18 = tail(sub(x, y), 1)
+ x <= T_18
else :
- node T_19 = subw(y, x)
- y := T_19
+ node T_19 = tail(sub(y, x), 1)
+ y <= T_19
when e :
- x := a
- y := b
- z := x
+ x <= a
+ y <= b
+ z <= x
node T_20 = eq(y, UInt<1>(0))
- v := T_20
+ v <= T_20
; CHECK: circuit GCD :
; CHECK: module GCD :
@@ -34,19 +34,21 @@ circuit GCD :
; CHECK: output v : UInt<1>
; CHECK: input a : UInt<16>
; CHECK: input b : UInt<16>
-; CHECK: reg x : UInt<16>, clk, reset
-; CHECK: reg y : UInt<16>, clk, reset
+; CHECK: reg x : UInt<16>, clk with :
+; CHECK: reset => (UInt<1>("h0"), x)
+; CHECK: reg y : UInt<16>, clk with :
+; CHECK: reset => (UInt<1>("h0"), y)
; CHECK: node T_17 = gt(x, y)
; CHECK: when T_17 :
-; CHECK: node T_18 = subw(x, y)
-; CHECK: x := T_18
+; CHECK: node T_18 = tail(sub(x, y), 1)
+; CHECK: x <= T_18
; CHECK: else :
-; CHECK: node T_19 = subw(y, x)
-; CHECK: y := T_19
+; CHECK: node T_19 = tail(sub(y, x), 1)
+; CHECK: y <= T_19
; CHECK: when e :
-; CHECK: x := a
-; CHECK: y := b
-; CHECK: z := x
-; CHECK: node T_20 = eq(y, UInt("h0"))
-; CHECK: v := T_20
+; CHECK: x <= a
+; CHECK: y <= b
+; CHECK: z <= x
+; CHECK: node T_20 = eq(y, UInt<1>("h0"))
+; CHECK: v <= T_20