diff options
| -rw-r--r-- | test/parser/bundle.fir | 53 | ||||
| -rw-r--r-- | test/parser/gcd.fir | 44 |
2 files changed, 50 insertions, 47 deletions
diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir index e0db4a7f..dae02d2a 100644 --- a/test/parser/bundle.fir +++ b/test/parser/bundle.fir @@ -1,43 +1,44 @@ ; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s + circuit top : module top : wire z : { x : UInt, flip y: SInt} - z.x := UInt(1) - z.y := SInt(1) + z.x <= UInt(1) + z.y <= SInt(1) node x = z.x node y = z.y wire a : UInt<3>[10] - a[0] := UInt(1) - a[1] := UInt(1) - a[2] := UInt(1) - a[3] := UInt(1) - a[4] := UInt(1) - a[5] := UInt(1) - a[6] := UInt(1) - a[7] := UInt(1) - a[8] := UInt(1) - a[9] := UInt(1) + a[0] <= UInt(1) + a[1] <= UInt(1) + a[2] <= UInt(1) + a[3] <= UInt(1) + a[4] <= UInt(1) + a[5] <= UInt(1) + a[6] <= UInt(1) + a[7] <= UInt(1) + a[8] <= UInt(1) + a[9] <= UInt(1) node b = a[2] - read accessor c = a[UInt(3)] + node c = a[UInt(3)] ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire z : { x : UInt, flip y : SInt} -; CHECK: z.x := UInt("h1") -; CHECK: z.y := SInt("h1") +; CHECK: z.x <= UInt("h1") +; CHECK: z.y <= SInt("h1") ; CHECK: node x = z.x ; CHECK: node y = z.y ; CHECK: wire a : UInt<3>[10] -; CHECK: a[0] := UInt("h1") -; CHECK: a[1] := UInt("h1") -; CHECK: a[2] := UInt("h1") -; CHECK: a[3] := UInt("h1") -; CHECK: a[4] := UInt("h1") -; CHECK: a[5] := UInt("h1") -; CHECK: a[6] := UInt("h1") -; CHECK: a[7] := UInt("h1") -; CHECK: a[8] := UInt("h1") -; CHECK: a[9] := UInt("h1") +; CHECK: a[0] <= UInt("h1") +; CHECK: a[1] <= UInt("h1") +; CHECK: a[2] <= UInt("h1") +; CHECK: a[3] <= UInt("h1") +; CHECK: a[4] <= UInt("h1") +; CHECK: a[5] <= UInt("h1") +; CHECK: a[6] <= UInt("h1") +; CHECK: a[7] <= UInt("h1") +; CHECK: a[8] <= UInt("h1") +; CHECK: a[9] <= UInt("h1") ; CHECK: node b = a[2] -; CHECK: read accessor c = a[UInt("h3")] +; CHECK: node c = a[UInt("h3")] diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir index fad3b41d..e0958a7a 100644 --- a/test/parser/gcd.fir +++ b/test/parser/gcd.fir @@ -9,21 +9,21 @@ circuit GCD : input a : UInt<16> input b : UInt<16> - reg x : UInt<16>,clk,reset - reg y : UInt<16>,clk,reset + reg x : UInt<16>,clk + reg y : UInt<16>,clk node T_17 = gt(x, y) when T_17 : - node T_18 = subw(x, y) - x := T_18 + node T_18 = tail(sub(x, y), 1) + x <= T_18 else : - node T_19 = subw(y, x) - y := T_19 + node T_19 = tail(sub(y, x), 1) + y <= T_19 when e : - x := a - y := b - z := x + x <= a + y <= b + z <= x node T_20 = eq(y, UInt<1>(0)) - v := T_20 + v <= T_20 ; CHECK: circuit GCD : ; CHECK: module GCD : @@ -34,19 +34,21 @@ circuit GCD : ; CHECK: output v : UInt<1> ; CHECK: input a : UInt<16> ; CHECK: input b : UInt<16> -; CHECK: reg x : UInt<16>, clk, reset -; CHECK: reg y : UInt<16>, clk, reset +; CHECK: reg x : UInt<16>, clk with : +; CHECK: reset => (UInt<1>("h0"), x) +; CHECK: reg y : UInt<16>, clk with : +; CHECK: reset => (UInt<1>("h0"), y) ; CHECK: node T_17 = gt(x, y) ; CHECK: when T_17 : -; CHECK: node T_18 = subw(x, y) -; CHECK: x := T_18 +; CHECK: node T_18 = tail(sub(x, y), 1) +; CHECK: x <= T_18 ; CHECK: else : -; CHECK: node T_19 = subw(y, x) -; CHECK: y := T_19 +; CHECK: node T_19 = tail(sub(y, x), 1) +; CHECK: y <= T_19 ; CHECK: when e : -; CHECK: x := a -; CHECK: y := b -; CHECK: z := x -; CHECK: node T_20 = eq(y, UInt("h0")) -; CHECK: v := T_20 +; CHECK: x <= a +; CHECK: y <= b +; CHECK: z <= x +; CHECK: node T_20 = eq(y, UInt<1>("h0")) +; CHECK: v <= T_20 |