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-rw-r--r--test/integration/GCDTester.fir24
-rw-r--r--test/integration/MemTester.fir22
-rw-r--r--test/integration/RightShiftTester.fir38
3 files changed, 42 insertions, 42 deletions
diff --git a/test/integration/GCDTester.fir b/test/integration/GCDTester.fir
index 335c573e..f236ecdc 100644
--- a/test/integration/GCDTester.fir
+++ b/test/integration/GCDTester.fir
@@ -1,16 +1,16 @@
circuit GCDTester :
module DecoupledGCD :
- input clk : Clock
+ input clock : Clock
input reset : UInt<1>
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : UInt<32>, b : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}
io is invalid
- reg busy : UInt<1>, clk with :
+ reg busy : UInt<1>, clock with :
reset => (reset, UInt<1>("h0"))
- reg done : UInt<1>, clk with :
+ reg done : UInt<1>, clock with :
reset => (reset, UInt<1>("h0"))
- reg x : UInt<32>, clk with :
+ reg x : UInt<32>, clock with :
reset => (UInt<1>("h0"), x)
- reg y : UInt<32>, clk with :
+ reg y : UInt<32>, clock with :
reset => (UInt<1>("h0"), y)
node T_40 = eq(busy, UInt<1>("h0"))
io.in.ready <= T_40
@@ -48,15 +48,15 @@ circuit GCDTester :
io.out.bits <= x
module GCDTester :
- input clk : Clock
+ input clock : Clock
input reset : UInt<1>
output io : { }
io is invalid
inst dut of DecoupledGCD
dut.io is invalid
- dut.clk <= clk
+ dut.clock <= clock
dut.reset <= reset
- reg count : UInt<4>, clk with :
+ reg count : UInt<4>, clock with :
reset => (reset, UInt<4>("h9"))
wire a : UInt<7>[10]
a[0] <= UInt<6>("h2e")
@@ -92,7 +92,7 @@ circuit GCDTester :
z[8] <= UInt<1>("h1")
z[9] <= UInt<1>("h1")
dut.io.out.ready <= UInt<1>("h0")
- reg en : UInt<1>, clk with :
+ reg en : UInt<1>, clock with :
reset => (reset, UInt<1>("h1"))
dut.io.in.bits.a <= a[count]
dut.io.in.bits.b <= b[count]
@@ -112,16 +112,16 @@ circuit GCDTester :
when T_91 :
node T_93 = eq(reset, UInt<1>("h0"))
when T_93 :
- printf(clk, UInt<1>("h1"), "Assertion failed\n at GCDTester.scala:38 assert( dut.io.out.bits === z(count) )\n")
+ printf(clock, UInt<1>("h1"), "Assertion failed\n at GCDTester.scala:38 assert( dut.io.out.bits === z(count) )\n")
skip
- stop(clk, UInt<1>("h1"), 1)
+ stop(clock, UInt<1>("h1"), 1)
skip
skip
node T_95 = eq(count, UInt<1>("h0"))
when T_95 :
node T_97 = eq(reset, UInt<1>("h0"))
when T_97 :
- stop(clk, UInt<1>("h1"), 0)
+ stop(clock, UInt<1>("h1"), 0)
skip
skip
node T_99 = eq(T_95, UInt<1>("h0"))
diff --git a/test/integration/MemTester.fir b/test/integration/MemTester.fir
index 451ec5d3..f3d04be4 100644
--- a/test/integration/MemTester.fir
+++ b/test/integration/MemTester.fir
@@ -1,17 +1,17 @@
circuit MemTester :
module ReadWrite :
- input clk : Clock
+ input clock : Clock
input reset : UInt<1>
- reg n : UInt<32>, clk with :
+ reg n : UInt<32>, clock with :
reset => (reset, UInt(0))
- reg wmode : UInt<1>, clk with :
+ reg wmode : UInt<1>, clock with :
reset => (reset, UInt(1))
wmode <= not(wmode)
- reg addr : UInt<5>, clk with :
+ reg addr : UInt<5>, clock with :
reset => (reset, UInt(0))
when eq(wmode, UInt(0)) :
@@ -25,7 +25,7 @@ circuit MemTester :
write-latency => 1
readwriter => rw
read-under-write => undefined
- m.rw.clk <= clk
+ m.rw.clk <= clock
m.rw.addr <= addr
m.rw.wmode <= wmode
m.rw.wdata <= n
@@ -35,21 +35,21 @@ circuit MemTester :
when not(reset) :
when eq(wmode, UInt(0)) :
when neq(m.rw.rdata, n) :
- printf(clk, UInt(1), "Assertion failed! m.rw.rdata has the wrong value!\n")
- stop(clk, UInt(1), 1)
+ printf(clock, UInt(1), "Assertion failed! m.rw.rdata has the wrong value!\n")
+ stop(clock, UInt(1), 1)
module MemTester :
- input clk : Clock
+ input clock : Clock
input reset : UInt<1>
- reg count : UInt<32>, clk with :
+ reg count : UInt<32>, clock with :
reset => (reset, UInt(100))
count <= tail(sub(count, UInt(1)), 1)
inst rwMod of ReadWrite
- rwMod.clk <= clk
+ rwMod.clock <= clock
rwMod.reset <= reset
when eq(count, UInt(0)) :
- stop(clk, UInt(1), 0)
+ stop(clock, UInt(1), 0)
diff --git a/test/integration/RightShiftTester.fir b/test/integration/RightShiftTester.fir
index b73b98ff..f15a1239 100644
--- a/test/integration/RightShiftTester.fir
+++ b/test/integration/RightShiftTester.fir
@@ -1,6 +1,6 @@
circuit RightShiftTester :
module RightShift :
- input clk : Clock
+ input clock : Clock
input reset : UInt<1>
output io : {flip i : UInt<1>, flip j : SInt<1>, i_shifted : UInt, j_shifted : SInt, k_shifted : UInt, l_shifted : UInt, m_shifted : SInt, n_shifted : SInt, o_shifted : UInt}
@@ -27,16 +27,16 @@ circuit RightShiftTester :
io.o_shifted <= T_28
module RightShiftTester :
- input clk : Clock
+ input clock : Clock
input reset : UInt<1>
output io : {}
io is invalid
inst dut of RightShift
dut.io is invalid
- dut.clk <= clk
+ dut.clock <= clock
dut.reset <= reset
- reg T_6 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
+ reg T_6 : UInt<2>, clock with : (reset => (reset, UInt<2>("h00")))
when UInt<1>("h01") :
node T_8 = eq(T_6, UInt<2>("h03"))
node T_10 = and(UInt<1>("h00"), T_8)
@@ -49,7 +49,7 @@ circuit RightShiftTester :
when done :
node T_18 = eq(reset, UInt<1>("h00"))
when T_18 :
- stop(clk, UInt<1>(1), 0)
+ stop(clock, UInt<1>(1), 0)
skip
skip
dut.io.i <= UInt<1>("h01")
@@ -61,9 +61,9 @@ circuit RightShiftTester :
when T_26 :
node T_28 = eq(reset, UInt<1>("h00"))
when T_28 :
- printf(clk, UInt<1>(1), "Assertion failed\n at RightShift.scala:47 assert(dut.io.i_shifted === UInt(0))\n")
+ printf(clock, UInt<1>(1), "Assertion failed\n at RightShift.scala:47 assert(dut.io.i_shifted === UInt(0))\n")
skip
- stop(clk, UInt<1>(1), 1)
+ stop(clock, UInt<1>(1), 1)
skip
skip
node T_30 = eq(dut.io.j_shifted, asSInt(UInt<1>("h01")))
@@ -73,9 +73,9 @@ circuit RightShiftTester :
when T_34 :
node T_36 = eq(reset, UInt<1>("h00"))
when T_36 :
- printf(clk, UInt<1>(1), "Assertion failed\n at RightShift.scala:48 assert(dut.io.j_shifted === SInt(-1))\n")
+ printf(clock, UInt<1>(1), "Assertion failed\n at RightShift.scala:48 assert(dut.io.j_shifted === SInt(-1))\n")
skip
- stop(clk, UInt<1>(1), 1)
+ stop(clock, UInt<1>(1), 1)
skip
skip
node T_38 = eq(dut.io.k_shifted, UInt<1>("h00"))
@@ -85,9 +85,9 @@ circuit RightShiftTester :
when T_42 :
node T_44 = eq(reset, UInt<1>("h00"))
when T_44 :
- printf(clk, UInt<1>(1), "Assertion failed\n at RightShift.scala:49 assert(dut.io.k_shifted === UInt(0))\n")
+ printf(clock, UInt<1>(1), "Assertion failed\n at RightShift.scala:49 assert(dut.io.k_shifted === UInt(0))\n")
skip
- stop(clk, UInt<1>(1), 1)
+ stop(clock, UInt<1>(1), 1)
skip
skip
node T_46 = eq(dut.io.l_shifted, UInt<1>("h00"))
@@ -97,9 +97,9 @@ circuit RightShiftTester :
when T_50 :
node T_52 = eq(reset, UInt<1>("h00"))
when T_52 :
- printf(clk, UInt<1>(1), "Assertion failed\n at RightShift.scala:50 assert(dut.io.l_shifted === UInt(0))\n")
+ printf(clock, UInt<1>(1), "Assertion failed\n at RightShift.scala:50 assert(dut.io.l_shifted === UInt(0))\n")
skip
- stop(clk, UInt<1>(1), 1)
+ stop(clock, UInt<1>(1), 1)
skip
skip
node T_54 = eq(dut.io.m_shifted, asSInt(UInt<1>("h01")))
@@ -109,9 +109,9 @@ circuit RightShiftTester :
when T_58 :
node T_60 = eq(reset, UInt<1>("h00"))
when T_60 :
- printf(clk, UInt<1>(1), "Assertion failed\n at RightShift.scala:51 assert(dut.io.m_shifted === SInt(-1))\n")
+ printf(clock, UInt<1>(1), "Assertion failed\n at RightShift.scala:51 assert(dut.io.m_shifted === SInt(-1))\n")
skip
- stop(clk, UInt<1>(1), 1)
+ stop(clock, UInt<1>(1), 1)
skip
skip
node T_62 = eq(dut.io.n_shifted, asSInt(UInt<1>("h00")))
@@ -121,9 +121,9 @@ circuit RightShiftTester :
when T_66 :
node T_68 = eq(reset, UInt<1>("h00"))
when T_68 :
- printf(clk, UInt<1>(1), "Assertion failed\n at RightShift.scala:52 assert(dut.io.n_shifted === SInt(0))\n")
+ printf(clock, UInt<1>(1), "Assertion failed\n at RightShift.scala:52 assert(dut.io.n_shifted === SInt(0))\n")
skip
- stop(clk, UInt<1>(1), 1)
+ stop(clock, UInt<1>(1), 1)
skip
skip
node T_70 = eq(dut.io.o_shifted, UInt<5>("h012"))
@@ -133,9 +133,9 @@ circuit RightShiftTester :
when T_74 :
node T_76 = eq(reset, UInt<1>("h00"))
when T_76 :
- printf(clk, UInt<1>(1), "Assertion failed\n at RightShift.scala:53 assert(dut.io.o_shifted === UInt(18))\n")
+ printf(clock, UInt<1>(1), "Assertion failed\n at RightShift.scala:53 assert(dut.io.o_shifted === UInt(18))\n")
skip
- stop(clk, UInt<1>(1), 1)
+ stop(clock, UInt<1>(1), 1)
skip
skip
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 12:09:00 +0000