8 files changed, 10 insertions, 10 deletions
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
index f8840f46..bf5b330e 100644
--- a/test/features/BulkConnect.fir
+++ b/test/features/BulkConnect.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Lower To Ground
 circuit Top : 
   module Top : 
diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir
index 13cdfcf9..146d11b9 100644
--- a/test/features/ExModule.fir
+++ b/test/features/ExModule.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 circuit Top : 
   module Top : 
     output z : UInt<4>
diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir
index 30c59fb9..0d49cf2a 100644
--- a/test/features/InitializeVec.fir
+++ b/test/features/InitializeVec.fir
@@ -1,8 +1,8 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit Tst : 
   module Tst : 
-    output in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}
+    input in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}
     output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4]
     
     in.ready := UInt<1>(1)
diff --git a/test/features/Link.fir b/test/features/Link.fir
index 190341f2..721f4727 100644
--- a/test/features/Link.fir
+++ b/test/features/Link.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -m /Users/cusgadmin/code/stanza/firrtl/test/features/Queue.fir -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -m /Users/cusgadmin/code/stanza/firrtl/test/features/Queue.fir -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Lower To Ground
 circuit Top : 
   module Top : 
diff --git a/test/features/Long.fir b/test/features/Long.fir
index e03ab091..1b5f0905 100644
--- a/test/features/Long.fir
+++ b/test/features/Long.fir
@@ -1,6 +1,6 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done
 circuit Top : 
   module Top : 
     wire a : UInt
-    a := UInt(4261441663)
+    a := UInt("h4261441663")
diff --git a/test/features/Queue.fir b/test/features/Queue.fir
index 345d2a44..07132d94 100644
--- a/test/features/Queue.fir
+++ b/test/features/Queue.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 ; CHECK: Done!
 circuit Queue :
   module Queue :
diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
index 4714ad4f..9690f2d1 100644
--- a/test/features/SeqMem.fir
+++ b/test/features/SeqMem.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit Top : 
   module Top : 
diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir
index cbbb01f1..9665c153 100644
--- a/test/features/TwoClocks.fir
+++ b/test/features/TwoClocks.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 circuit Top : 
   module Top : 
     input clk1 : Clock