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Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 33cb70db..9a2bc11f 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -141,6 +141,7 @@ class EmitVerilogFromLowFirrtl (val writer: Writer) extends Transform with Simpl passes.RemoveValidIf, passes.ConstProp, passes.PadWidths, + passes.ConstProp, passes.VerilogWrap, passes.SplitExpressions, passes.CommonSubexpressionElimination, |