diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/antlr4/FIRRTL.g4 | 7 | ||||
| -rw-r--r-- | src/main/scala/firrtl/Visitor.scala | 2 |
2 files changed, 2 insertions, 7 deletions
diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4 index 8bdbbea3..c49bb948 100644 --- a/src/main/antlr4/FIRRTL.g4 +++ b/src/main/antlr4/FIRRTL.g4 @@ -27,11 +27,6 @@ import firrtl.LexerHelper; * PARSER RULES *------------------------------------------------------------------*/ -/* TODO - * - Add [info] support (all over the place) - * - Add support for extmodule -*/ - // Does there have to be at least one module? circuit : 'circuit' id ':' info? INDENT module* DEDENT @@ -90,7 +85,7 @@ simple_reset reset_block : INDENT simple_reset info? NEWLINE DEDENT - | '(' + simple_reset + ')' + | '(' simple_reset ')' ; stmt diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala index 5dda1df3..bcf60b53 100644 --- a/src/main/scala/firrtl/Visitor.scala +++ b/src/main/scala/firrtl/Visitor.scala @@ -255,7 +255,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] { val (reset, init) = { val rb = ctx.reset_block() if (rb != null) { - val sr = rb.simple_reset(0).simple_reset0() + val sr = rb.simple_reset.simple_reset0() (visitExp(sr.exp(0)), visitExp(sr.exp(1))) } else |