diff options
| author | Leway Colin | 2019-06-28 11:35:24 +0800 |
|---|---|---|
| committer | mergify[bot] | 2019-06-28 03:35:24 +0000 |
| commit | 6a466c2c15579e63bf54aa5b999f5876f335ac6f (patch) | |
| tree | 1f53e968d6a76b82a975a0a8a0a3ee2216a1efd1 /src | |
| parent | babc04f7960e04a2b1868e40ab204ca3a6d66332 (diff) | |
Fix typo (#1101)
* Fix typo
* Fix simple_rest typo
Co-Authored-By: jack koenig <jack.koenig3@gmail.com>
* simple_reset isn't a Array due to 'simple_reset+' change to 'simple_reset' in FIRRTL.g4
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/antlr4/FIRRTL.g4 | 7 | ||||
| -rw-r--r-- | src/main/scala/firrtl/Visitor.scala | 2 |
2 files changed, 2 insertions, 7 deletions
diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4 index 8bdbbea3..c49bb948 100644 --- a/src/main/antlr4/FIRRTL.g4 +++ b/src/main/antlr4/FIRRTL.g4 @@ -27,11 +27,6 @@ import firrtl.LexerHelper; * PARSER RULES *------------------------------------------------------------------*/ -/* TODO - * - Add [info] support (all over the place) - * - Add support for extmodule -*/ - // Does there have to be at least one module? circuit : 'circuit' id ':' info? INDENT module* DEDENT @@ -90,7 +85,7 @@ simple_reset reset_block : INDENT simple_reset info? NEWLINE DEDENT - | '(' + simple_reset + ')' + | '(' simple_reset ')' ; stmt diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala index 5dda1df3..bcf60b53 100644 --- a/src/main/scala/firrtl/Visitor.scala +++ b/src/main/scala/firrtl/Visitor.scala @@ -255,7 +255,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] { val (reset, init) = { val rb = ctx.reset_block() if (rb != null) { - val sr = rb.simple_reset(0).simple_reset0() + val sr = rb.simple_reset.simple_reset0() (visitExp(sr.exp(0)), visitExp(sr.exp(1))) } else |