diff options
Diffstat (limited to 'src/test')
12 files changed, 16 insertions, 20 deletions
diff --git a/src/test/scala/firrtl/testutils/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala index 4dc2d642..53a8e1e3 100644 --- a/src/test/scala/firrtl/testutils/FirrtlSpec.scala +++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala @@ -70,7 +70,8 @@ object RenameTop extends Transform { } } -trait FirrtlRunners extends BackendCompilationUtilities { +trait FirrtlRunners { + import BackendCompilationUtilities._ val cppHarnessResourceName: String = "/firrtl/testTop.cpp" diff --git a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala index 33661df9..94f90e61 100644 --- a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala +++ b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala @@ -6,11 +6,12 @@ import firrtl._ import firrtl.transforms._ import firrtl.testutils._ import annotations._ + import java.io.File import java.nio.file.Paths - import firrtl.options.Dependency import firrtl.stage.FirrtlStage +import firrtl.util.BackendCompilationUtilities.createTestDirectory class CheckCombLoopsSpec extends LeanTransformSpec(Seq(Dependency[CheckCombLoops])) { "Loop-free circuit" should "not throw an exception" in { diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala index db8b6e79..07a2212f 100644 --- a/src/test/scala/firrtlTests/DCETests.scala +++ b/src/test/scala/firrtlTests/DCETests.scala @@ -9,6 +9,7 @@ import firrtl.annotations._ import firrtl.passes.memlib.SimpleTransform import firrtl.stage.FirrtlStage import firrtl.testutils._ +import firrtl.util.BackendCompilationUtilities.createTestDirectory import java.io.File import java.nio.file.Paths diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala index 4913b09d..2249764c 100644 --- a/src/test/scala/firrtlTests/IntegrationSpec.scala +++ b/src/test/scala/firrtlTests/IntegrationSpec.scala @@ -5,6 +5,7 @@ package firrtlTests import firrtl._ import firrtl.stage.FirrtlStage import firrtl.testutils._ +import firrtl.util.BackendCompilationUtilities._ import java.io.File diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala index 7ce128be..019221f6 100644 --- a/src/test/scala/firrtlTests/StringSpec.scala +++ b/src/test/scala/firrtlTests/StringSpec.scala @@ -4,9 +4,9 @@ package firrtlTests import firrtl.ir.StringLit import firrtl.testutils._ +import firrtl.util.BackendCompilationUtilities._ import java.io._ - import scala.sys.process._ import annotation.tailrec import org.scalacheck._ diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index e533255a..4c09c083 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -11,7 +11,7 @@ import firrtl.passes._ import firrtl.transforms.{CombineCats, NoDCEAnnotation} import firrtl.testutils._ import firrtl.testutils.FirrtlCheckers._ -import firrtl.util.BackendCompilationUtilities +import firrtl.util.BackendCompilationUtilities._ import scala.sys.process.{Process, ProcessLogger} @@ -1366,7 +1366,7 @@ class EmittedMacroSpec extends FirrtlPropSpec { "+define+FIRRTL_AFTER_INITIAL=initial begin $fwrite(32'h80000002, \"printing from FIRRTL_AFTER_INITIAL macro\\n\"); end" ) - BackendCompilationUtilities.verilogToCpp(prefix, testDir, List.empty, harness, extraCmdLineArgs = cmdLineArgs) #&& + verilogToCpp(prefix, testDir, List.empty, harness, extraCmdLineArgs = cmdLineArgs) #&& cppToExe(prefix, testDir) ! loggingProcessLogger diff --git a/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala b/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala index 84872ebe..1842e1e1 100644 --- a/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala +++ b/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala @@ -3,9 +3,9 @@ package firrtlTests.execution import java.io.File - import firrtl.ir._ import firrtl.testutils._ +import firrtl.util.BackendCompilationUtilities.createTestDirectory sealed trait SimpleTestCommand case class Step(n: Int) extends SimpleTestCommand diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala index fe6e1832..01da57a0 100644 --- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala +++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala @@ -3,12 +3,11 @@ package firrtlTests.execution import java.io.File - import firrtl._ import firrtl.ir._ - import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage} import firrtl.options.TargetDirAnnotation +import firrtl.util.BackendCompilationUtilities._ /** * Mixing in this trait causes a SimpleExecutionTest to be run in Verilog simulation. diff --git a/src/test/scala/firrtlTests/options/phases/GetIncludesSpec.scala b/src/test/scala/firrtlTests/options/phases/GetIncludesSpec.scala index 54129269..9049ec59 100644 --- a/src/test/scala/firrtlTests/options/phases/GetIncludesSpec.scala +++ b/src/test/scala/firrtlTests/options/phases/GetIncludesSpec.scala @@ -18,7 +18,7 @@ case object C extends NoTargetAnnotation case object D extends NoTargetAnnotation case object E extends NoTargetAnnotation -class GetIncludesSpec extends AnyFlatSpec with Matchers with BackendCompilationUtilities with firrtl.testutils.Utils { +class GetIncludesSpec extends AnyFlatSpec with Matchers with firrtl.testutils.Utils { val dir = new File("test_run_dir/GetIncludesSpec") dir.mkdirs() diff --git a/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala b/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala index 240724ab..80324c99 100644 --- a/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala +++ b/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala @@ -7,12 +7,10 @@ import org.scalatest.featurespec.AnyFeatureSpec import org.scalatest.matchers.should.Matchers import java.io.{File, PrintWriter} - import firrtl.{BuildInfo, FileUtils} - import firrtl.stage.{FirrtlMain, WarnNoScalaVersionDeprecation} import firrtl.stage.transforms.CheckScalaVersion -import firrtl.util.BackendCompilationUtilities +import firrtl.util.BackendCompilationUtilities._ import org.scalatest.featurespec.AnyFeatureSpec import org.scalatest.matchers.should.Matchers @@ -21,12 +19,7 @@ import org.scalatest.matchers.should.Matchers * This test uses the [[org.scalatest.FeatureSpec FeatureSpec]] intentionally as this test exercises the top-level * interface and is more suitable to an Acceptance Testing style. */ -class FirrtlMainSpec - extends AnyFeatureSpec - with GivenWhenThen - with Matchers - with firrtl.testutils.Utils - with BackendCompilationUtilities { +class FirrtlMainSpec extends AnyFeatureSpec with GivenWhenThen with Matchers with firrtl.testutils.Utils { /** Parameterizes one test of [[FirrtlMain]]. Running the [[FirrtlMain]] `main` with certain args should produce * certain files and not produce others. diff --git a/src/test/scala/firrtlTests/transforms/LegalizeReductions.scala b/src/test/scala/firrtlTests/transforms/LegalizeReductions.scala index ce904e28..797e366d 100644 --- a/src/test/scala/firrtlTests/transforms/LegalizeReductions.scala +++ b/src/test/scala/firrtlTests/transforms/LegalizeReductions.scala @@ -5,7 +5,7 @@ package firrtlTests.transforms import firrtl._ import firrtl.ir.StringLit import firrtl.testutils._ - +import firrtl.util.BackendCompilationUtilities._ import org.scalatest.flatspec.AnyFlatSpec import java.io.File diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala index 050c57c8..321a9fea 100644 --- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala +++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala @@ -4,7 +4,6 @@ package firrtlTests package transforms import java.io._ - import firrtl._ import firrtl.ir.{GroundType, IntWidth, Type} import firrtl.Parser @@ -12,6 +11,7 @@ import firrtl.annotations.{CircuitName, ComponentName, ModuleName, Target} import firrtl.stage.FirrtlStage import firrtl.transforms.TopWiring._ import firrtl.testutils._ +import firrtl.util.BackendCompilationUtilities.createTestDirectory trait TopWiringTestsCommon extends FirrtlRunners { |