diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogEmitterTests.scala | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 9840229e..42f0bf85 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -373,10 +373,13 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { val renderer = emitter.getRenderer(module, moduleMap)(writer) - renderer.emitVerilogBind("BindsToTest", """ - |$readmemh("file", memory); - | - |""".stripMargin) + renderer.emitVerilogBind( + "BindsToTest", + """ + |$readmemh("file", memory); + | + |""".stripMargin + ) val lines = writer.toString.split("\n") val outString = writer.toString |