diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/wiring/WiringUtils.scala | 8 | ||||
| -rw-r--r-- | src/main/scala/firrtl/stage/phases/Checks.scala | 10 | ||||
| -rw-r--r-- | src/main/scala/logger/phases/Checks.scala | 6 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogEmitterTests.scala | 11 |
4 files changed, 23 insertions, 12 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala index 5e8f8616..59b042f5 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala @@ -56,7 +56,9 @@ case class Lineage( def shortSerialize(tab: String): String = s""" |$tab name: $name, - |$tab children: ${children.map(c => tab + " " + c._2.shortSerialize(tab + " "))} + |$tab children: ${children.map(c => + tab + " " + c._2.shortSerialize(tab + " ") + )} |""".stripMargin def foldLeft[B](z: B)(op: (B, (String, Lineage)) => B): B = @@ -71,7 +73,9 @@ case class Lineage( |$tab sharedParent: $sharedParent, |$tab addPort: $addPort |$tab cons: $cons - |$tab children: ${children.map(c => tab + " " + c._2.serialize(tab + " "))} + |$tab children: ${children.map(c => + tab + " " + c._2.serialize(tab + " ") + )} |""".stripMargin } diff --git a/src/main/scala/firrtl/stage/phases/Checks.scala b/src/main/scala/firrtl/stage/phases/Checks.scala index 6576d311..24cfa0a3 100644 --- a/src/main/scala/firrtl/stage/phases/Checks.scala +++ b/src/main/scala/firrtl/stage/phases/Checks.scala @@ -55,10 +55,12 @@ class Checks extends Phase { /* Only one FIRRTL input can exist */ if (inF.size + inS.size + inC.size > 1) { - throw new OptionsException(s"""|Multiply defined input FIRRTL sources. More than one of the following was found: - | - an input file (${inF.size} times): -i, --input-file, FirrtlFileAnnotation - | - FIRRTL source (${inS.size} times): --firrtl-source, FirrtlSourceAnnotation - | - FIRRTL circuit (${inC.size} times): FirrtlCircuitAnnotation""".stripMargin) + throw new OptionsException( + s"""|Multiply defined input FIRRTL sources. More than one of the following was found: + | - an input file (${inF.size} times): -i, --input-file, FirrtlFileAnnotation + | - FIRRTL source (${inS.size} times): --firrtl-source, FirrtlSourceAnnotation + | - FIRRTL circuit (${inC.size} times): FirrtlCircuitAnnotation""".stripMargin + ) } /* Specifying an output file and one-file-per module conflict */ diff --git a/src/main/scala/logger/phases/Checks.scala b/src/main/scala/logger/phases/Checks.scala index 0109c7ad..707118e3 100644 --- a/src/main/scala/logger/phases/Checks.scala +++ b/src/main/scala/logger/phases/Checks.scala @@ -40,8 +40,10 @@ object Checks extends Phase { ) } if (lf.size > 1) { - throw new LoggerException(s"""|At most one log file can be specified, but found ${lf.size} combinations of: - | - an options or annotation: -ltf, --log-to-file, --log-file, LogFileAnnotation""".stripMargin) + throw new LoggerException( + s"""|At most one log file can be specified, but found ${lf.size} combinations of: + | - an options or annotation: -ltf, --log-to-file, --log-file, LogFileAnnotation""".stripMargin + ) } annotations } diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 9840229e..42f0bf85 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -373,10 +373,13 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { val renderer = emitter.getRenderer(module, moduleMap)(writer) - renderer.emitVerilogBind("BindsToTest", """ - |$readmemh("file", memory); - | - |""".stripMargin) + renderer.emitVerilogBind( + "BindsToTest", + """ + |$readmemh("file", memory); + | + |""".stripMargin + ) val lines = writer.toString.split("\n") val outString = writer.toString |