diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogEmitterTests.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 7adc490f..60ab983b 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -11,6 +11,7 @@ import firrtl.transforms.VerilogRename import firrtl.transforms.CombineCats import firrtl.testutils._ import firrtl.testutils.FirrtlCheckers._ +import firrtl.util.BackendCompilationUtilities import scala.sys.process.{Process, ProcessLogger} @@ -891,7 +892,7 @@ class EmittedMacroSpec extends FirrtlPropSpec { "+define+FIRRTL_AFTER_INITIAL=initial begin $fwrite(32'h80000002, \"printing from FIRRTL_AFTER_INITIAL macro\\n\"); end" ) - verilogToCppWithExtraCmdLineArgs(prefix, testDir, List.empty, harness, extraCmdLineArgs = cmdLineArgs) #&& + BackendCompilationUtilities.verilogToCpp(prefix, testDir, List.empty, harness, extraCmdLineArgs = cmdLineArgs) #&& cppToExe(prefix, testDir) ! loggingProcessLogger |