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authorDeborah Soung2020-05-08 13:50:25 -0700
committerGitHub2020-05-08 20:50:25 +0000
commit72c48bbf9f6b3a0458f793bca6bff739917b8231 (patch)
tree6fb73be1713a5d4545a7f4fd92c474748823723c /src/test
parentbed5e2d3d7820129a137abcbc8b5e1ab7e6f7939 (diff)
deprecating BackendCompilationUtilities trait for object (#1575)
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/VerilogEmitterTests.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 7adc490f..60ab983b 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -11,6 +11,7 @@ import firrtl.transforms.VerilogRename
import firrtl.transforms.CombineCats
import firrtl.testutils._
import firrtl.testutils.FirrtlCheckers._
+import firrtl.util.BackendCompilationUtilities
import scala.sys.process.{Process, ProcessLogger}
@@ -891,7 +892,7 @@ class EmittedMacroSpec extends FirrtlPropSpec {
"+define+FIRRTL_AFTER_INITIAL=initial begin $fwrite(32'h80000002, \"printing from FIRRTL_AFTER_INITIAL macro\\n\"); end"
)
- verilogToCppWithExtraCmdLineArgs(prefix, testDir, List.empty, harness, extraCmdLineArgs = cmdLineArgs) #&&
+ BackendCompilationUtilities.verilogToCpp(prefix, testDir, List.empty, harness, extraCmdLineArgs = cmdLineArgs) #&&
cppToExe(prefix, testDir) !
loggingProcessLogger