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Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index cee2c15d..dac8a40f 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -60,11 +60,12 @@ class UnitTests extends FirrtlFlatSpec { | input y: {a : UInt<1>} | output x: {a : UInt<1>, b : UInt<1>} | x <= y""".stripMargin - intercept[PassExceptions] { + val thrown = intercept[PassExceptions] { passes.foldLeft(parse(input)) { (c: Circuit, p: Pass) => p.run(c) } } + assert(thrown.getMessage contains "Type mismatch. Cannot connect") } "Initializing a register with a different type" should "throw an exception" in { |