diff options
| author | Colin Schmidt | 2016-04-19 09:51:24 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-05-24 10:42:18 -0700 |
| commit | 243ff24f8eb9aae18bb0c7afe4f4c1e6cd66c084 (patch) | |
| tree | 7b35106bb2b01747538b664fbb78bf8d87967039 /src/test | |
| parent | 89cbd83265c5bfb3968865ebaddf79efb4f47050 (diff) | |
add better type mismatch error message
also check for it int unittest
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index cee2c15d..dac8a40f 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -60,11 +60,12 @@ class UnitTests extends FirrtlFlatSpec { | input y: {a : UInt<1>} | output x: {a : UInt<1>, b : UInt<1>} | x <= y""".stripMargin - intercept[PassExceptions] { + val thrown = intercept[PassExceptions] { passes.foldLeft(parse(input)) { (c: Circuit, p: Pass) => p.run(c) } } + assert(thrown.getMessage contains "Type mismatch. Cannot connect") } "Initializing a register with a different type" should "throw an exception" in { |
