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-rw-r--r--src/test/scala/firrtlTests/execution/VerilogExecution.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
index 17eecc65..060554c0 100644
--- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala
+++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
@@ -25,8 +25,8 @@ trait VerilogExecution extends TestExecution {
copyResourceToFile(cppHarnessResourceName, harness)
// Make and run Verilog simulation
- verilogToCpp(c.main, testDir, Nil, harness).!
- cppToExe(c.main, testDir).!
+ verilogToCpp(c.main, testDir, Nil, harness) #&&
+ cppToExe(c.main, testDir) ! loggingProcessLogger
assert(executeExpectingSuccess(c.main, testDir))
}
}