diff options
Diffstat (limited to 'src')
6 files changed, 23 insertions, 18 deletions
diff --git a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala index beb44ad0..20a65895 100644 --- a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala +++ b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala @@ -7,11 +7,13 @@ import java.nio.file.Files import java.text.SimpleDateFormat import java.util.Calendar +import logger.LazyLogging + import firrtl.FileUtils import scala.sys.process.{ProcessBuilder, ProcessLogger, _} -trait BackendCompilationUtilities { +trait BackendCompilationUtilities extends LazyLogging { /** Parent directory for tests */ lazy val TestDirectory = new File("test_run_dir") @@ -21,6 +23,9 @@ trait BackendCompilationUtilities { format.format(now) } + def loggingProcessLogger: ProcessLogger = + ProcessLogger(logger.info(_), logger.warn(_)) + /** * Copy the contents of a resource to a destination file. * @param name the name of the resource @@ -151,7 +156,7 @@ trait BackendCompilationUtilities { s"""-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=V$dutFile -DVL_USER_FINISH -include V$dutFile.h""", "-Mdir", dir.getAbsolutePath, "--exe", cppHarness.getAbsolutePath) - System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex + logger.info(s"${command.mkString(" ")}") // scalastyle:ignore regex command } @@ -167,8 +172,9 @@ trait BackendCompilationUtilities { val e = Process(s"./V$prefix", dir) ! ProcessLogger(line => { triggered = triggered || (assertionMessageSupplied && line.contains(assertionMsg)) - System.out.println(line) // scalastyle:ignore regex - }) + logger.info(line) // scalastyle:ignore regex + }, + logger.warn(_)) // Fail if a line contained an assertion or if we get a non-zero exit code // or, we get a SIGABRT (assertion failure) and we didn't provide a specific assertion message triggered || (e != 0 && (e != 134 || !assertionMessageSupplied)) diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala index b4f61dfd..88a39a01 100644 --- a/src/test/scala/firrtlTests/DriverSpec.scala +++ b/src/test/scala/firrtlTests/DriverSpec.scala @@ -498,8 +498,8 @@ class VcdSuppressionSpec extends FirrtlFlatSpec { val harness = new File(testDir, s"top.cpp") copyResourceToFile(cppHarnessResourceName, harness) - verilogToCpp(prefix, testDir, Seq.empty, harness, suppress).! - cppToExe(prefix, testDir).! + verilogToCpp(prefix, testDir, Seq.empty, harness, suppress) #&& + cppToExe(prefix, testDir) ! loggingProcessLogger assert(executeExpectingSuccess(prefix, testDir)) diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala index 1ff5b72f..ee8dfe8e 100644 --- a/src/test/scala/firrtlTests/FirrtlSpec.scala +++ b/src/test/scala/firrtlTests/FirrtlSpec.scala @@ -7,18 +7,16 @@ import java.security.Permission import logger.LazyLogging -import scala.sys.process._ import org.scalatest._ import org.scalatest.prop._ import firrtl._ import firrtl.ir._ -import firrtl.Parser.{IgnoreInfo, UseInfo} -import firrtl.analyses.{GetNamespace, InstanceGraph, ModuleNamespaceAnnotation} +import firrtl.Parser.UseInfo +import firrtl.analyses.{GetNamespace, ModuleNamespaceAnnotation} import firrtl.annotations._ import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation, RenameModules} import firrtl.util.BackendCompilationUtilities -import scala.collection.mutable class CheckLowForm extends SeqTransform { def inputForm = LowForm @@ -146,8 +144,9 @@ trait FirrtlRunners extends BackendCompilationUtilities { file } - verilogToCpp(prefix, testDir, verilogFiles, harness).! - cppToExe(prefix, testDir).! + verilogToCpp(prefix, testDir, verilogFiles, harness) #&& + cppToExe(prefix, testDir) ! + loggingProcessLogger assert(executeExpectingSuccess(prefix, testDir)) } } diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala index b7fd0084..732cd501 100644 --- a/src/test/scala/firrtlTests/IntegrationSpec.scala +++ b/src/test/scala/firrtlTests/IntegrationSpec.scala @@ -42,8 +42,8 @@ class GCDSplitEmissionExecutionTest extends FirrtlFlatSpec { copyResourceToFile(cppHarnessResourceName, harness) // topFile will be compiled by Verilator command by default but we need to also include dutFile - verilogToCpp(top, testDir, Seq(dutFile), harness).! - cppToExe(top, testDir).! + verilogToCpp(top, testDir, Seq(dutFile), harness) #&& + cppToExe(top, testDir) ! loggingProcessLogger assert(executeExpectingSuccess(top, testDir)) } } diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala index 208d9e6c..aaf2a584 100644 --- a/src/test/scala/firrtlTests/StringSpec.scala +++ b/src/test/scala/firrtlTests/StringSpec.scala @@ -23,8 +23,8 @@ class PrintfSpec extends FirrtlPropSpec { val harness = new File(testDir, s"top.cpp") copyResourceToFile(cppHarnessResourceName, harness) - verilogToCpp(prefix, testDir, Seq(), harness).! - cppToExe(prefix, testDir).! + verilogToCpp(prefix, testDir, Seq(), harness) #&& + cppToExe(prefix, testDir) ! loggingProcessLogger // Check for correct Printf: // Count up from 0, match decimal, hex, and binary diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala index 17eecc65..060554c0 100644 --- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala +++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala @@ -25,8 +25,8 @@ trait VerilogExecution extends TestExecution { copyResourceToFile(cppHarnessResourceName, harness) // Make and run Verilog simulation - verilogToCpp(c.main, testDir, Nil, harness).! - cppToExe(c.main, testDir).! + verilogToCpp(c.main, testDir, Nil, harness) #&& + cppToExe(c.main, testDir) ! loggingProcessLogger assert(executeExpectingSuccess(c.main, testDir)) } } |