diff options
Diffstat (limited to 'src/test/scala/firrtlTests/LoweringCompilersSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index 75f2ea02..82750fdf 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -354,6 +354,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { val tm = (new TransformManager(Seq(Dependency[firrtl.MinimumVerilogEmitter], Dependency[Transforms.LowToLow]))) val patches = Seq( Add(63, Seq( + Dependency(firrtl.transforms.formal.ConvertAsserts), Dependency[firrtl.transforms.formal.RemoveVerificationStatements], Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) ) @@ -367,6 +368,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { val tm = (new TransformManager(Seq(Dependency[firrtl.VerilogEmitter], Dependency[Transforms.LowToLow]))) val patches = Seq( Add(70, Seq( + Dependency(firrtl.transforms.formal.ConvertAsserts), Dependency[firrtl.transforms.formal.RemoveVerificationStatements], Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) ) |