1 files changed, 2 insertions, 5 deletions
diff --git a/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala b/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala
index 7475d6cb..44fd8e92 100644
--- a/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala
+++ b/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala
@@ -40,10 +40,8 @@ class RtlilEquivalenceTest extends AnyFlatSpec with LazyLogging {
     val verilogFile = testDir.toString + "/" + fileName + ".v"
 
     val log = ProcessLogger(
-      msg => {
-        println(msg)
-      },
-      logger.error(_)
+      logger.info(_),
+      logger.warn(_)
     )
 
     val yosysArgs = Array(
@@ -67,7 +65,6 @@ class RtlilEquivalenceTest extends AnyFlatSpec with LazyLogging {
       "equiv_induct -seq 1 -undef;",
       "equiv_status -assert"
     )
-    println(yosysArgs.mkString(" "))
     val yosysRet = Process(Seq("yosys", "-p", yosysArgs.mkString(" "))).run(log).exitValue()
     assert(yosysRet == 0, s"Unable to prove equivalence of design ${name}.")
   }