diff options
| -rw-r--r-- | src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala | 7 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/SeparateWriteClocksSpec.scala | 1 |
2 files changed, 2 insertions, 6 deletions
diff --git a/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala b/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala index 7475d6cb..44fd8e92 100644 --- a/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala +++ b/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala @@ -40,10 +40,8 @@ class RtlilEquivalenceTest extends AnyFlatSpec with LazyLogging { val verilogFile = testDir.toString + "/" + fileName + ".v" val log = ProcessLogger( - msg => { - println(msg) - }, - logger.error(_) + logger.info(_), + logger.warn(_) ) val yosysArgs = Array( @@ -67,7 +65,6 @@ class RtlilEquivalenceTest extends AnyFlatSpec with LazyLogging { "equiv_induct -seq 1 -undef;", "equiv_status -assert" ) - println(yosysArgs.mkString(" ")) val yosysRet = Process(Seq("yosys", "-p", yosysArgs.mkString(" "))).run(log).exitValue() assert(yosysRet == 0, s"Unable to prove equivalence of design ${name}.") } diff --git a/src/test/scala/firrtlTests/SeparateWriteClocksSpec.scala b/src/test/scala/firrtlTests/SeparateWriteClocksSpec.scala index 476a3ae2..8342c563 100644 --- a/src/test/scala/firrtlTests/SeparateWriteClocksSpec.scala +++ b/src/test/scala/firrtlTests/SeparateWriteClocksSpec.scala @@ -58,7 +58,6 @@ class SeparateWriteClocksSpec extends FirrtlFlatSpec { | m.w_b.mask <= UInt(1) | m.w_b.data <= wdata_b""".stripMargin) - println(result.circuit.serialize) result should containLine("m.r.clk <= clk") result should containLine("m.w_a.clk <= m_w_a_clk") result should containLine("m.w_b.clk <= m_w_b_clk") |