diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala | 5 | ||||
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveReset.scala | 10 |
2 files changed, 12 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala index af8996eb..f48e4846 100644 --- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala +++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala @@ -787,13 +787,12 @@ class VerilogEmitter extends SeqTransform with Emitter { } else { // Asynchronous Reset assert(reset.tpe == AsyncResetType, "Error! Synchronous reset should have been removed!") val tv = init - val InfoExpr(finfo, fv) = netlist(r) - // TODO add register info argument and build a MultiInfo to pass + val InfoExpr(info, fv) = netlist(r) asyncResetAlwaysBlocks += ( ( clk, reset, - addUpdate(NoInfo, Mux(reset, tv, fv, mux_type_and_widths(tv, fv)), Seq.empty) + addUpdate(info, Mux(reset, tv, fv, mux_type_and_widths(tv, fv)), Seq.empty) ) ) } diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala index 62b341cd..f1434ad2 100644 --- a/src/main/scala/firrtl/transforms/RemoveReset.scala +++ b/src/main/scala/firrtl/transforms/RemoveReset.scala @@ -50,6 +50,7 @@ object RemoveReset extends Transform with DependencyAPIMigration { private def onModule(m: DefModule, isPreset: String => Boolean): DefModule = { val resets = mutable.HashMap.empty[String, Reset] + val asyncResets = mutable.HashMap.empty[String, Reset] val invalids = computeInvalids(m) def onStmt(stmt: Statement): Statement = { stmt match { @@ -77,12 +78,21 @@ object RemoveReset extends Transform with DependencyAPIMigration { // Add register reset to map resets(rname) = Reset(reset, init, info) reg.copy(reset = Utils.zero, init = WRef(reg)) + case reg @ DefRegister(info, rname, _, _, reset, init) if reset.tpe == AsyncResetType => + asyncResets(rname) = Reset(reset, init, info) + reg case Connect(info, ref @ WRef(rname, _, RegKind, _), expr) if resets.contains(rname) => val reset = resets(rname) val muxType = Utils.mux_type_and_widths(reset.value, expr) // Use reg source locator for mux enable and true value since that's where they're defined val infox = MultiInfo(reset.info, reset.info, info) Connect(infox, ref, Mux(reset.cond, reset.value, expr, muxType)) + case Connect(info, ref @ WRef(rname, _, RegKind, _), expr) if asyncResets.contains(rname) => + val reset = asyncResets(rname) + // The `muxType` for async always blocks is located in [[VerilogEmitter.VerilogRender.regUpdate]]: + // addUpdate(info, Mux(reset, tv, fv, mux_type_and_widths(tv, fv)), Seq.empty) + val infox = MultiInfo(reset.info, reset.info, info) + Connect(infox, ref, expr) case other => other.map(onStmt) } } |