diff options
| -rw-r--r-- | src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala | 5 | ||||
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveReset.scala | 10 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogEmitterTests.scala | 16 |
3 files changed, 28 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala index af8996eb..f48e4846 100644 --- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala +++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala @@ -787,13 +787,12 @@ class VerilogEmitter extends SeqTransform with Emitter { } else { // Asynchronous Reset assert(reset.tpe == AsyncResetType, "Error! Synchronous reset should have been removed!") val tv = init - val InfoExpr(finfo, fv) = netlist(r) - // TODO add register info argument and build a MultiInfo to pass + val InfoExpr(info, fv) = netlist(r) asyncResetAlwaysBlocks += ( ( clk, reset, - addUpdate(NoInfo, Mux(reset, tv, fv, mux_type_and_widths(tv, fv)), Seq.empty) + addUpdate(info, Mux(reset, tv, fv, mux_type_and_widths(tv, fv)), Seq.empty) ) ) } diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala index 62b341cd..f1434ad2 100644 --- a/src/main/scala/firrtl/transforms/RemoveReset.scala +++ b/src/main/scala/firrtl/transforms/RemoveReset.scala @@ -50,6 +50,7 @@ object RemoveReset extends Transform with DependencyAPIMigration { private def onModule(m: DefModule, isPreset: String => Boolean): DefModule = { val resets = mutable.HashMap.empty[String, Reset] + val asyncResets = mutable.HashMap.empty[String, Reset] val invalids = computeInvalids(m) def onStmt(stmt: Statement): Statement = { stmt match { @@ -77,12 +78,21 @@ object RemoveReset extends Transform with DependencyAPIMigration { // Add register reset to map resets(rname) = Reset(reset, init, info) reg.copy(reset = Utils.zero, init = WRef(reg)) + case reg @ DefRegister(info, rname, _, _, reset, init) if reset.tpe == AsyncResetType => + asyncResets(rname) = Reset(reset, init, info) + reg case Connect(info, ref @ WRef(rname, _, RegKind, _), expr) if resets.contains(rname) => val reset = resets(rname) val muxType = Utils.mux_type_and_widths(reset.value, expr) // Use reg source locator for mux enable and true value since that's where they're defined val infox = MultiInfo(reset.info, reset.info, info) Connect(infox, ref, Mux(reset.cond, reset.value, expr, muxType)) + case Connect(info, ref @ WRef(rname, _, RegKind, _), expr) if asyncResets.contains(rname) => + val reset = asyncResets(rname) + // The `muxType` for async always blocks is located in [[VerilogEmitter.VerilogRender.regUpdate]]: + // addUpdate(info, Mux(reset, tv, fv, mux_type_and_widths(tv, fv)), Seq.empty) + val infox = MultiInfo(reset.info, reset.info, info) + Connect(infox, ref, expr) case other => other.map(onStmt) } } diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 4c09c083..1a40cc8f 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -717,6 +717,22 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { result should containLine("assign z = x == y;") } + it should "show line numbers for AsyncReset regUpdate" in { + val result = compileBody( + """input clock : Clock + |input reset : AsyncReset + |output io : { flip in : UInt<1>, out : UInt<1>} + | + |reg valid : UInt<1>, clock with : + | reset => (reset, UInt<1>("h0")) @[Playground.scala 11:22] + |valid <= io.in @[Playground.scala 12:9] + |io.out <= valid @[Playground.scala 13:10]""".stripMargin + ) + result should containLine("if (reset) begin // @[Playground.scala 11:22]") + result should containLine("valid <= 1'h0; // @[Playground.scala 11:22]") + result should containLine("valid <= io_in; // @[Playground.scala 12:9]") + } + it should "subtract positive literals instead of adding negative literals" in { val compiler = new VerilogCompiler val result = compileBody( |