diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/clocklist')
| -rw-r--r-- | src/main/scala/firrtl/passes/clocklist/ClockList.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockList.scala b/src/main/scala/firrtl/passes/clocklist/ClockList.scala index fcc3cd5e..43583726 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockList.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockList.scala @@ -44,7 +44,7 @@ class ClockList(top: String, writer: Writer) extends Pass { val modulesToInline = (c.modules.collect { case Module(_, n, _, _) if n != top => ModuleName(n, CircuitName(c.main)) }).toSet val inlineTransform = new InlineInstances val inlinedCircuit = inlineTransform.run(onlyClockCircuit, modulesToInline, Set(), Seq()).circuit - val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError(Some("no top module"))) + val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError("no top module")) // Build a hashmap of connections to use for getOrigins val connects = getConnects(topModule) |