diff options
Diffstat (limited to 'TODO')
| -rw-r--r-- | TODO | 16 |
1 files changed, 14 insertions, 2 deletions
@@ -9,7 +9,6 @@ Parser Update parser and update tests Make instances always male, flip the bundles on declaration dlsh,drsh -move Infer-Widths to before vec expansion? ======== Update Core ========== Add source locaters @@ -40,13 +39,19 @@ Width inference ======== Other Passes ======== constant folding (partial eval) pass + Get rid of unnecessary pads + push pad into literal common subexpression elimination pass +deadcode elimination Verilog backend +Eliminate skips ======== Consultations ======== Stephen: width equality pin stephen on an example +Patrick: + move Infer-Widths to before vec expansion? ======== Think About ======== subword accesses @@ -59,7 +64,6 @@ Multi-streams for print statements/asserts (Jack) Consider def female node. (Patrick) Talk to palmer/patrick about how writing passes is going to be supported Figure out how widths propogate for all updated primops (Adam) -Add partial bulk connect (Scott, Stephen) Add FIFOs to the IR (Palmer) Think about supporting generic primops on bundles and vecs (Adam) (wait until front-end more completed) Union Types @@ -105,3 +109,11 @@ Schedulable Nack Scheduler +======== Notes ======== +Only for MUXES can width inference go backwards: + reg r : UInt<5> + r := MUX(p,UInt<?>(1),UInt<?>(2)) + ==> + reg r : UInt<5> + r := MUX(p,UInt<5>(1),UInt<5>(2)) + |