diff options
| -rw-r--r-- | TODO | 16 | ||||
| -rw-r--r-- | src/main/stanza/primop.stanza | 19 |
2 files changed, 25 insertions, 10 deletions
@@ -9,7 +9,6 @@ Parser Update parser and update tests Make instances always male, flip the bundles on declaration dlsh,drsh -move Infer-Widths to before vec expansion? ======== Update Core ========== Add source locaters @@ -40,13 +39,19 @@ Width inference ======== Other Passes ======== constant folding (partial eval) pass + Get rid of unnecessary pads + push pad into literal common subexpression elimination pass +deadcode elimination Verilog backend +Eliminate skips ======== Consultations ======== Stephen: width equality pin stephen on an example +Patrick: + move Infer-Widths to before vec expansion? ======== Think About ======== subword accesses @@ -59,7 +64,6 @@ Multi-streams for print statements/asserts (Jack) Consider def female node. (Patrick) Talk to palmer/patrick about how writing passes is going to be supported Figure out how widths propogate for all updated primops (Adam) -Add partial bulk connect (Scott, Stephen) Add FIFOs to the IR (Palmer) Think about supporting generic primops on bundles and vecs (Adam) (wait until front-end more completed) Union Types @@ -105,3 +109,11 @@ Schedulable Nack Scheduler +======== Notes ======== +Only for MUXES can width inference go backwards: + reg r : UInt<5> + r := MUX(p,UInt<?>(1),UInt<?>(2)) + ==> + reg r : UInt<5> + r := MUX(p,UInt<5>(1),UInt<5>(2)) + diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index a6b42e7c..e88a6b8e 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -329,20 +329,12 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : PAD-S-OP : IntWidth(consts(e)[0]) NEG-U-OP : IntWidth(1) NEG-S-OP : IntWidth(1) - AS-UINT-U-OP : max-args-w - AS-UINT-S-OP : max-args-w - AS-SINT-U-OP : max-args-w - AS-SINT-S-OP : max-args-w SHIFT-LEFT-U-OP : PlusWidth(max-args-w,IntWidth(consts(e)[0])) SHIFT-LEFT-S-OP : PlusWidth(max-args-w,IntWidth(consts(e)[0])) SHIFT-RIGHT-U-OP : MinusWidth(max-args-w,IntWidth(consts(e)[0])) SHIFT-RIGHT-S-OP : MinusWidth(max-args-w,IntWidth(consts(e)[0])) CONVERT-U-OP : PlusWidth(max-args-w,IntWidth(1)) CONVERT-S-OP : max-args-w - BIT-NOT-OP : max-args-w - BIT-AND-OP : max-args-w - BIT-OR-OP : max-args-w - BIT-XOR-OP : max-args-w BIT-SELECT-OP : IntWidth(1) BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1]) else : @@ -355,6 +347,17 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : all-equal(List(w-var,tail(map(width!,args(e))))) CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1])) + BIT-NOT-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-AND-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-OR-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-XOR-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-AND-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-OR-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-XOR-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-UINT-U-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-UINT-S-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-SINT-U-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-SINT-S-OP : all-equal(List(w-var,map(width!,args(e)))) add(v,WGeq(w-var,w*)) match(type(e)) : |