diff options
| -rw-r--r-- | src/main/stanza/chirrtl.stanza | 7 | ||||
| -rw-r--r-- | test/passes/to-verilog/rdwr-mem.fir | 61 | ||||
| -rw-r--r-- | test/passes/to-verilog/wr-mem.fir | 40 |
3 files changed, 75 insertions, 33 deletions
diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza index f9971323..59f6e359 100644 --- a/src/main/stanza/chirrtl.stanza +++ b/src/main/stanza/chirrtl.stanza @@ -163,12 +163,19 @@ defn infer-mdir (c:Circuit) -> Circuit : [MInfer,MInfer] : error("Shouldn't be here") [MInfer,MWrite] : MWrite [MInfer,MRead] : MRead + [MInfer,MReadWrite] : MReadWrite [MWrite,MInfer] : error("Shouldn't be here") [MWrite,MWrite] : MWrite [MWrite,MRead] : MReadWrite + [MWrite,MReadWrite] : MReadWrite [MRead,MInfer] : error("Shouldn't be here") [MRead,MWrite] : MReadWrite [MRead,MRead] : MRead + [MRead,MReadWrite] : MReadWrite + [MReadWrite,MInfer] : error("Shouldn't be here") + [MReadWrite,MWrite] : MReadWrite + [MReadWrite,MRead] : MReadWrite + [MReadWrite,MReadWrite] : MReadWrite mports[name(e)] = new_mport_dir e (e) : e diff --git a/test/passes/to-verilog/rdwr-mem.fir b/test/passes/to-verilog/rdwr-mem.fir index d056ecf6..e382b3b5 100644 --- a/test/passes/to-verilog/rdwr-mem.fir +++ b/test/passes/to-verilog/rdwr-mem.fir @@ -9,8 +9,9 @@ circuit top : input wen : UInt<1> input clk : Clock - smem m : UInt<32>[4],clk - rdwr accessor c = m[index] + smem m : UInt<32>[4] + infer mport c = m[index],clk + rdata is invalid when ren : rdata <= c when wen : @@ -18,30 +19,50 @@ circuit top : ; CHECK: module top( -; CHECK: output [31:0] rdata, -; CHECK: input [1:0] index, -; CHECK: input [0:0] ren, -; CHECK: input [0:0] clk +; CHECK: output [31:0] rdata, +; CHECK: input [31:0] wdata, +; CHECK: input [1:0] index, +; CHECK: input ren, +; CHECK: input wen, +; CHECK: input clk ; CHECK: ); -; CHECK: wire [31:0] c; -; CHECK: reg [31:0] m [0:3]; -; CHECK: reg [1:0] index_1; +; CHECK: reg [31:0] m [0:3]; +; CHECK: wire [31:0] m_c_rdata; +; CHECK: wire [1:0] m_c_raddr; +; CHECK: wire m_c_ren; +; CHECK: wire [31:0] m_c_wdata; +; CHECK: wire [1:0] m_c_waddr; +; CHECK: wire m_c_wmask; +; CHECK: wire m_c_wen; +; CHECK: wire m_c_clk; +; CHECK: reg [1:0] GEN_2; +; CHECK: reg GEN_3; +; CHECK: reg [1:0] GEN_0; +; CHECK: reg [31:0] GEN_1; +; CHECK: assign rdata = m_c_rdata; +; CHECK: assign m_c_clk = clk; +; CHECK: assign m_c_raddr = index; +; CHECK: assign m_c_ren = 1'h1; +; CHECK: assign m_c_rdata = m[GEN_2]; +; CHECK: assign m_c_wdata = wen ? wdata : GEN_1; +; CHECK: assign m_c_waddr = index; +; CHECK: assign m_c_wmask = wen ? 1'h1 : 1'h0; +; CHECK: assign m_c_wen = 1'h1; ; CHECK: `ifndef SYNTHESIS ; CHECK: integer initvar; ; CHECK: initial begin ; CHECK: #0.002; -; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) +; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) ; CHECK: m[initvar] = {1{$random}}; -; CHECK: index_1 = {1{$random}}; +; CHECK: GEN_0 = {1{$random}}; +; CHECK: GEN_1 = {1{$random}}; ; CHECK: end ; CHECK: `endif -; CHECK: assign rdata = m[index_1]; -; CHECK: always @(posedge clk) begin -; CHECK: if(ren) begin -; CHECK: index_1 <= index; -; CHECK: end else if(wen) begin -; CHECK: m[index] <= wdata; -; CHECK: end -; CHECK: end +; CHECK: always @(posedge m_c_clk) begin +; CHECK: GEN_2 <= m_c_raddr; +; CHECK: GEN_3 <= m_c_ren; +; CHECK: if(m_c_wen & m_c_wmask) begin +; CHECK: m[m_c_waddr] <= m_c_wdata; +; CHECK: end +; CHECK: end ; CHECK: endmodule - diff --git a/test/passes/to-verilog/wr-mem.fir b/test/passes/to-verilog/wr-mem.fir index b21491aa..06745812 100644 --- a/test/passes/to-verilog/wr-mem.fir +++ b/test/passes/to-verilog/wr-mem.fir @@ -7,30 +7,44 @@ circuit top : input wen : UInt<1> input clk : Clock - smem m : UInt<32>[4],clk - write accessor c = m[index] + smem m : UInt<32>[4] + write mport c = m[index],clk when wen : c <= wdata ; CHECK: module top( -; CHECK: input [31:0] wdata, -; CHECK: input [1:0] index, -; CHECK: input [0:0] wen, -; CHECK: input [0:0] clk +; CHECK: input [31:0] wdata, +; CHECK: input [1:0] index, +; CHECK: input wen, +; CHECK: input clk ; CHECK: ); -; CHECK: reg [31:0] m [0:3]; +; CHECK: reg [31:0] m [0:3]; +; CHECK: wire [31:0] m_c_data; +; CHECK: wire [1:0] m_c_addr; +; CHECK: wire m_c_mask; +; CHECK: wire m_c_en; +; CHECK: wire m_c_clk; +; CHECK: reg [1:0] GEN_0; +; CHECK: reg [31:0] GEN_1; +; CHECK: assign m_c_data = wen ? wdata : GEN_1; +; CHECK: assign m_c_addr = index; +; CHECK: assign m_c_mask = wen ? 1'h1 : 1'h0; +; CHECK: assign m_c_en = 1'h1; +; CHECK: assign m_c_clk = clk; ; CHECK: `ifndef SYNTHESIS ; CHECK: integer initvar; ; CHECK: initial begin ; CHECK: #0.002; -; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) +; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) ; CHECK: m[initvar] = {1{$random}}; +; CHECK: GEN_0 = {1{$random}}; +; CHECK: GEN_1 = {1{$random}}; ; CHECK: end ; CHECK: `endif -; CHECK: always @(posedge clk) begin -; CHECK: if(wen) begin -; CHECK: m[index] <= wdata; -; CHECK: end -; CHECK: end +; CHECK: always @(posedge m_c_clk) begin +; CHECK: if(m_c_en & m_c_mask) begin +; CHECK: m[m_c_addr] <= m_c_data; +; CHECK: end +; CHECK: end ; CHECK: endmodule |