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| author | Albert Magyar | 2021-02-25 13:28:17 -0800 |
|---|---|---|
| committer | GitHub | 2021-02-25 13:28:17 -0800 |
| commit | 89e9ab0bb0fd3f1f4a79eaf6209727684a2fa23f (patch) | |
| tree | 6d163e0d9be96f3046daccf16adc1ddb8b59db2a /utils/bin | |
| parent | edb91f7bc613026f824519786c3ce25740bb21c3 (diff) | |
Emit space after 'if' for all Verilog conditional synchronous assignments (#2091)
Diffstat (limited to 'utils/bin')
0 files changed, 0 insertions, 0 deletions