diff options
| -rw-r--r-- | src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala index 3ecd1279..f1650ad7 100644 --- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala +++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala @@ -756,7 +756,7 @@ class VerilogEmitter extends SeqTransform with Emitter { val lines = noResetAlwaysBlocks.getOrElseUpdate(clk, ArrayBuffer[Seq[Any]]()) if (weq(en, one)) lines += Seq(e, " <= ", value, ";") else { - lines += Seq("if(", en, ") begin") + lines += Seq("if (", en, ") begin") lines += Seq(tab, e, " <= ", value, ";", info) lines += Seq("end") } |