Merge branch 'master' of github.com:ucb-bar/firrtl into new-low-firrtl

1 files changed, 18 insertions, 0 deletions

diff --git a/test/chisel3/Test.fir b/test/chisel3/Test.fir
new file mode 100644
index 00000000..f0d8f80e
--- /dev/null
+++ b/test/chisel3/Test.fir
@@ -0,0 +1,18 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit Test : 
+  module Test : 
+     input clk : Clock
+     input reset : UInt<1>
+     input falling : UInt<1>
+
+     reg hold : UInt<100>, clk, UInt(1)
+
+     hold := UInt("h42")
+     when reset :
+        hold := UInt("h7f")
+     else :
+        when falling :
+           hold := UInt("h8f")
+