Rewrote the initialize-register pass, now correctly implemented

with a new IR construct - Null. LetRec is not implemented, but is
marked with a TODO.

Test cases for this pass are now located in
test/passes/initialize-register

4 files changed, 137 insertions, 0 deletions

diff --git a/test/passes/initialize-register/begin.fir b/test/passes/initialize-register/begin.fir
new file mode 100644
index 00000000..9d4de49e
--- /dev/null
+++ b/test/passes/initialize-register/begin.fir
@@ -0,0 +1,22 @@
+; RUN: firrtl %s abcd | tee %s.out | FileCheck %s 
+
+         circuit top :
+            module top :
+               input a : UInt(16)
+               input b : UInt(16)
+               output z : UInt
+
+               reg r1 : UInt
+; CHECK:       wire [[R1:gen[0-9]*]] : UInt
+; CHECK:       n:[[R1]] := Null
+
+               reg r2 : UInt
+               r2.init := UInt(0)
+; CHECK:       wire [[R2:gen[0-9]*]] : UInt
+; CHECK-NOT:   reg:r2 := n:[[R2]]
+; CHECK:       n:[[R2]] := Null
+; CHECK:       n:[[R2]] := UInt(0)
+      
+; CHECK:       when port:reset :
+; CHECK-DAG:      reg:r1 := n:[[R1]]
+; CHECK-DAG:      reg:r2 := n:[[R2]]
diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir
new file mode 100644
index 00000000..e4749abe
--- /dev/null
+++ b/test/passes/initialize-register/when.fir
@@ -0,0 +1,40 @@
+; RUN: firrtl %s abcd | tee %s.out | FileCheck %s 
+; CHECK: circuit top :
+         circuit top :
+            module top :
+               input a : UInt(16)
+               input b : UInt(16)
+               output z : UInt
+               when greater(1, 2) :
+                  reg r1: UInt
+                  r1.init := UInt(12)
+; CHECK:          wire [[R1:gen[0-9]*]] : UInt
+; CHECK-NOT:      reg:r1 := n:[[R1]]
+; CHECK:          n:[[R1]] := Null
+; CHECK:          n:[[R1]] := UInt(12)
+; CHECK-NOT:      r1.init := UInt(12)
+                  reg r2: UInt
+; CHECK:          wire [[R2:gen[0-9]*]] : UInt
+; CHECK-NOT:      reg:r2 := n:[[R2]]
+; CHECK:          n:[[R2]] := Null
+
+; CHECK:          when port:reset :
+; CHECK-DAG:         reg:r2 := n:[[R2]]
+; CHECK-DAG:         reg:r1 := n:[[R1]]
+               else :
+                  reg r1: UInt
+                  r1.init := UInt(12)
+; CHECK:          wire [[R1:gen[0-9]*]] : UInt
+; CHECK-NOT:      reg:r1 := n:[[R1]]
+; CHECK:          n:[[R1]] := Null
+; CHECK:          n:[[R1]] := UInt(12)
+; CHECK-NOT:      r1.init := UInt(12)
+
+                  reg r2: UInt
+; CHECK:          wire [[R2:gen[0-9]*]] : UInt
+; CHECK-NOT:      reg:r2 := n:[[R2]]
+; CHECK:          n:[[R2]] := Null
+
+; CHECK:          when port:reset :
+; CHECK-DAG:         reg:r2 := n:[[R2]]
+; CHECK-DAG:         reg:r1 := n:[[R1]]
diff --git a/test/passes/make-explicit-reset/abc.fir b/test/passes/make-explicit-reset/abc.fir
new file mode 100644
index 00000000..caed07ab
--- /dev/null
+++ b/test/passes/make-explicit-reset/abc.fir
@@ -0,0 +1,27 @@
+; RUN: firrtl %s abc | tee %s.out | FileCheck %s
+
+circuit top :
+   module A :
+      ;CHECK: input reset : UInt(1)
+      input x : UInt(16)
+      output y : UInt(16)
+      inst b of B
+      ;CHECK: inst:b.reset := port:reset
+   module B :
+      input reset : UInt(1)
+      ;CHECK: input reset : UInt(1)
+      input x : UInt(16)
+      output y : UInt(16)
+      inst c of C
+      ;CHECK: inst:c.reset := port:reset
+   module C :
+      ;CHECK: input reset : UInt(1)
+      input a : UInt(16)
+      input b : UInt(16)
+   module top :
+      ;CHECK: input reset : UInt(1)
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst a of A
+      ;CHECK: inst:a.reset := port:reset
diff --git a/test/passes/resolve-kinds/ab.fir b/test/passes/resolve-kinds/ab.fir
new file mode 100644
index 00000000..e6f28c21
--- /dev/null
+++ b/test/passes/resolve-kinds/ab.fir
@@ -0,0 +1,48 @@
+; RUN: firrtl %s ab | tee %s.out | FileCheck %s
+
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output z : UInt
+      z := sub-mod(x, y)
+; CHECK: port:z := sub-mod(port:x, port:y)
+   module gcd :
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
+      x.init := UInt(0)
+      y.init := UInt(42)
+      when greater(x, y) :
+         inst s of subtracter
+         s.x := x
+; CHECK: inst:s.x := reg:x
+         s.y := y
+         x := s.z
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.z
+      when e :
+         x := a
+         y := b
+      v := equal(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst i of gcd
+; CHECK: inst i of module:gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+; CHECK: port:z := inst:i.z
+
+