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| author | azidar | 2016-01-27 15:21:36 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | d6468e562b184c38ce67530c513ee9c4af93ae9c (patch) | |
| tree | d247d00c59fb34e8888c7a9d4fc75867246604d2 /test/passes/split-exp | |
| parent | 0408e8692e77021edc21c361f514455cf6f85a16 (diff) | |
Added tests for previous commit
Diffstat (limited to 'test/passes/split-exp')
| -rw-r--r-- | test/passes/split-exp/split-and.fir | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/test/passes/split-exp/split-and.fir b/test/passes/split-exp/split-and.fir new file mode 100644 index 00000000..8eb4bdab --- /dev/null +++ b/test/passes/split-exp/split-and.fir @@ -0,0 +1,8 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s + +; CHECK: Done! +circuit Top : + module Top : + input a : SInt<2> + output c : UInt<2> + c <= and(a,asSInt(UInt(2))) |