diff options
| -rw-r--r-- | test/passes/split-exp/split-and.fir | 8 | ||||
| -rw-r--r-- | test/passes/to-verilog/signed-and.fir | 17 |
2 files changed, 25 insertions, 0 deletions
diff --git a/test/passes/split-exp/split-and.fir b/test/passes/split-exp/split-and.fir new file mode 100644 index 00000000..8eb4bdab --- /dev/null +++ b/test/passes/split-exp/split-and.fir @@ -0,0 +1,8 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s + +; CHECK: Done! +circuit Top : + module Top : + input a : SInt<2> + output c : UInt<2> + c <= and(a,asSInt(UInt(2))) diff --git a/test/passes/to-verilog/signed-and.fir b/test/passes/to-verilog/signed-and.fir new file mode 100644 index 00000000..ffb7bd23 --- /dev/null +++ b/test/passes/to-verilog/signed-and.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s + +circuit Top : + module Top : + input a : SInt<2> + output c : UInt<2> + c <= and(a,asSInt(UInt(2))) + +; CHECK: module Top( +; CHECK: input [1:0] a, +; CHECK: output [1:0] c +; CHECK: ); +; CHECK: wire [1:0] GEN_0; +; CHECK: assign c = $signed(a) & $signed(GEN_0); +; CHECK: assign GEN_0 = $signed(2'h2); +; CHECK: endmodule + |