Updated all tests to pass

2 files changed, 8 insertions, 5 deletions

diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 4d7772d9..c2a0df4a 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -6,8 +6,8 @@ circuit top :
       input x : UInt
       input y : UInt
       output z : UInt
-      z <= subw(x, y)
-      ;CHECK: z@<g:f> <= subw(x@<g:m>, y@<g:m>)
+      z <= tail(sub(x, y),1)
+      ;CHECK: z@<g:f> <= tail(sub(x@<g:m>, y@<g:m>)@<g:m>, 1)@<g:m>   
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -16,8 +16,10 @@ circuit top :
       input reset : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt,clk,reset,UInt(0)
-      reg y : UInt,clk,reset,UInt(42)
+      reg x : UInt,clk with :
+         reset => (reset,UInt(0))
+      reg y : UInt,clk with :
+         reset => (reset,UInt(42))
 ; CHECK: reg x : UInt
       when gt(x, y) :
       ;CHECK: when gt(x@<g:m>, y@<g:m>)@<g:m> :
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
index 0d0dd574..e91fa52e 100644
--- a/test/passes/resolve-genders/subbundle.fir
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -6,7 +6,8 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       wire w : { flip x : UInt<10>}
-      reg r : { flip x : UInt<10>},clk,reset,w
+      reg r : { flip x : UInt<10>},clk with :
+         reset => (reset,w)
       w <= r     ; CHECK r_x := w_x
       w.x <= r.x ; CHECK w_x := r_x
 ; CHECK: Finished Lower Types