diff options
| author | azidar | 2016-01-25 11:29:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-25 11:29:45 -0800 |
| commit | f6ea3dc1bb5efb4455fd3b995ced36add85a44c0 (patch) | |
| tree | dbc0135e3a4ef0ac387fa9fe02b6f7bba2d4dbe5 /test/passes/remove-accesses/bundle-vecs.fir | |
| parent | a637f4f0cedadf5e81fc9d9d3b1392daf99db603 (diff) | |
Changed tests to pass with change to postfix of generated name
Diffstat (limited to 'test/passes/remove-accesses/bundle-vecs.fir')
| -rw-r--r-- | test/passes/remove-accesses/bundle-vecs.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir index 13f9d8d6..e916bfa8 100644 --- a/test/passes/remove-accesses/bundle-vecs.fir +++ b/test/passes/remove-accesses/bundle-vecs.fir @@ -29,10 +29,10 @@ circuit top : ; CHECK: a[1].x <= UInt("h1") ; CHECK: a[1].y <= UInt("h1") ; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>} -; CHECK: wire GEN : UInt<32> -; CHECK: GEN <= a[0].x -; CHECK: when eqv(UInt("h1"), i) : GEN <= a[1].x -; CHECK: b.x <= GEN +; CHECK: wire GEN_0 : UInt<32> +; CHECK: GEN_0 <= a[0].x +; CHECK: when eqv(UInt("h1"), i) : GEN_0 <= a[1].x +; CHECK: b.x <= GEN_0 ; CHECK: wire GEN_1 : UInt<32> ; CHECK: when eqv(UInt("h0"), i) : a[0].y <= GEN_1 ; CHECK: when eqv(UInt("h1"), i) : a[1].y <= GEN_1 |