diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/lower-to-ground/register.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/lower-to-ground/register.fir')
| -rw-r--r-- | test/passes/lower-to-ground/register.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index 75b4fe88..99f63153 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -11,13 +11,13 @@ reg r1 : { x : UInt, y : SInt },clk,reset wire q : { x : UInt, y : SInt } - onreset r1 := q + onreset r1 <= q ; CHECK: reg r1{{[_$]+}}x : UInt ; CHECK: reg r1{{[_$]+}}y : SInt ; CHECK: wire q{{[_$]+}}x : UInt ; CHECK: wire q{{[_$]+}}y : SInt - ; CHECK: onreset r1{{[_$]+}}x := q{{[_$]+}}x - ; CHECK: onreset r1{{[_$]+}}y := q{{[_$]+}}y + ; CHECK: onreset r1{{[_$]+}}x <= q{{[_$]+}}x + ; CHECK: onreset r1{{[_$]+}}y <= q{{[_$]+}}y ; CHECK: Finished Lower To Ground |