diff options
| author | jackbackrack | 2015-05-14 13:39:56 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-05-14 13:39:56 -0700 |
| commit | 369a6d9ee974f7ca825174e053742e0d4f440575 (patch) | |
| tree | 1fa3fc4a103505d4b5eac777d320bc825dd90de5 /test/passes/jacktest | |
| parent | 54c33b61ff2c6da7fcd717885316604ecc559c25 (diff) | |
| parent | 521a4277bfc1d764dc9ee771c604200525e871cb (diff) | |
merge
Diffstat (limited to 'test/passes/jacktest')
| -rw-r--r-- | test/passes/jacktest/bundlewire.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/jacktest/bundlewire.fir b/test/passes/jacktest/bundlewire.fir index cd5b2dfe..cea54ed4 100644 --- a/test/passes/jacktest/bundlewire.fir +++ b/test/passes/jacktest/bundlewire.fir @@ -1,17 +1,17 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x X -p ct | tee %s.out | FileCheck %s ; CHECK: Expand Whens circuit TestLower : module Inst : - input x : UInt - output y : UInt + input data : { w : UInt , x : UInt } + input tag : { y : UInt, z : UInt } module TestLower : mem m : {data : { w : UInt , x : UInt } tag : { y : UInt, z : UInt }}[8] wire index : UInt accessor r = m[index] inst i of Inst - i.x := r + i.data := r.data ; CHECK: Finished Expand Whens |