diff options
| author | azidar | 2016-01-26 14:18:34 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 5ab30c681558d2a26000696e518ee5b28deb1303 (patch) | |
| tree | dcdfaeb3bcb42561e010928712218c8cd3a1b2c7 /test/passes/jacktest/ModuleVec.fir | |
| parent | 8c288f7b159b3f4ca1cb0d5c5012eb8fb52d5214 (diff) | |
Updated all tests to pass
Diffstat (limited to 'test/passes/jacktest/ModuleVec.fir')
| -rw-r--r-- | test/passes/jacktest/ModuleVec.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir index 9a8e7f2c..6f9b699b 100644 --- a/test/passes/jacktest/ModuleVec.fir +++ b/test/passes/jacktest/ModuleVec.fir @@ -5,13 +5,13 @@ circuit ModuleVec : input in : UInt<32> output out : UInt<32> - node T_33 = addw(in, UInt<1>(1)) + node T_33 = tail(add(in, UInt<1>(1)),1) out <= T_33 module PlusOne_25 : input in : UInt<32> output out : UInt<32> - node T_34 = addw(in, UInt<1>(1)) + node T_34 = tail(add(in, UInt<1>(1)),1) out <= T_34 module ModuleVec : input ins : UInt<32>[2] |