Fixed final bug. All tests pass. Accessors are a go.

7 files changed, 46 insertions, 26 deletions

diff --git a/test/passes/inline-indexers/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir
index c41794e3..28826056 100644
--- a/test/passes/inline-indexers/bundle-vecs.fir
+++ b/test/passes/inline-indexers/bundle-vecs.fir
@@ -1,6 +1,6 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 
-; CHECK: Expand Indexed Connects
+; CHECK: Inline Indexers
 circuit top :
    module top :
       wire i : UInt
@@ -20,16 +20,17 @@ circuit top :
 
 
       infer accessor b = a[i]
-      ; CHECK: wire b{{[_$]+}}x : UInt<32>
-      ; CHECK: wire b{{[_$]+}}y : UInt<32>
-      ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x
+      ; CHECK: wire b{{[_$]+}}x_1 : UInt<32>
       ; CHECK: node i_1 = i
-      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x      
+      ; CHECK: b{{[_$]+}}x_1 := a{{[_$]+}}0{{[_$]+}}x
+      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_1 := a{{[_$]+}}1{{[_$]+}}x      
+      ; CHECK: wire b{{[_$]+}}y_1 : UInt<32>
       ; CHECK: node i_2 = i
-      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y      
-      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y      
+      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_1
+      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_1
       j := b.x
       b.y := UInt(1)
       
-; CHECK: Finished Expand Indexed Connects
+; CHECK: Finished Inline Indexers
+; CHECK: Done!
 
diff --git a/test/passes/inline-indexers/simple.fir b/test/passes/inline-indexers/simple.fir
index ca65977b..ca186e97 100644
--- a/test/passes/inline-indexers/simple.fir
+++ b/test/passes/inline-indexers/simple.fir
@@ -12,8 +12,8 @@ circuit top :
       infer accessor a = m[i] 
       o := a
 
-;CHECK: a := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: a_1 := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
 
 
 
diff --git a/test/passes/inline-indexers/simple2.fir b/test/passes/inline-indexers/simple2.fir
index a334b626..3b7d92af 100644
--- a/test/passes/inline-indexers/simple2.fir
+++ b/test/passes/inline-indexers/simple2.fir
@@ -14,12 +14,12 @@ circuit top :
       o1 := a
       o2 := a
 
-;CHECK: wire a : UInt<32>
-;CHECK: a := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
 ;CHECK: wire a_1 : UInt<32>
 ;CHECK: a_1 := m$0
-;CHECK: when eqv(i_2, UInt("h1")) : a_1 := m$1
+;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
+;CHECK: wire a_2 : UInt<32>
+;CHECK: a_2 := m$0
+;CHECK: when eqv(i_2, UInt("h1")) : a_2 := m$1
 
 
 
diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir
index fd8d1418..688958a0 100644
--- a/test/passes/inline-indexers/simple3.fir
+++ b/test/passes/inline-indexers/simple3.fir
@@ -11,9 +11,9 @@ circuit top :
       infer accessor a = m[i] 
       a := in
 
-;CHECK: wire a : UInt<32>
-;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a
-;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a
+;CHECK: wire a_1 : UInt<32>
+;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_1
+;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_1
 
 
 
diff --git a/test/passes/inline-indexers/simple4.fir b/test/passes/inline-indexers/simple4.fir
index dce8f26f..df045456 100644
--- a/test/passes/inline-indexers/simple4.fir
+++ b/test/passes/inline-indexers/simple4.fir
@@ -13,11 +13,11 @@ circuit top :
       infer accessor a = m[i] 
       a.x := in.x
 
-;CHECK: wire a$x : UInt<32>
+;CHECK: wire a$x_1 : UInt<32>
 ;CHECK: node i_1 = i
-;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x
-;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x
-;CHECK: a$x := in$x
+;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x_1
+;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x_1
+;CHECK: a$x_1 := in$x
 ;CHECK: Finished Inline Indexers
 ;CHECK: Done!
 
diff --git a/test/passes/inline-indexers/simple5.fir b/test/passes/inline-indexers/simple5.fir
index 8cd7bec1..1da83cab 100644
--- a/test/passes/inline-indexers/simple5.fir
+++ b/test/passes/inline-indexers/simple5.fir
@@ -15,7 +15,7 @@ circuit top :
          o := a
 
 ;CHECK: when i :
-;CHECK: a := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: a_1 := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
 ;CHECK: Finished Inline Indexers
 ;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple6.fir b/test/passes/inline-indexers/simple6.fir
index 98b28611..e94efc7a 100644
--- a/test/passes/inline-indexers/simple6.fir
+++ b/test/passes/inline-indexers/simple6.fir
@@ -7,19 +7,38 @@ circuit top :
       input in : {x : UInt<32>, y : UInt<32>}
       wire m :{x : UInt<32>, y : UInt<32>}[2][2] 
       wire i : UInt
+      wire j : UInt
 
       m[0][0] := in
       m[1][0] := in
       m[0][1] := in
       m[1][1] := in
       i := UInt("h1")
+      j := UInt("h1")
 
       write accessor a = m[i] 
-      write accessor b = a[i] 
+      write accessor b = a[j] 
       b.x := value
 
-;CHECK: a := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: wire b$x_1 : UInt<32>
+;CHECK: node j_1 = j
+;CHECK: when eqv(j_1, UInt("h0")) :
+;CHECK:    wire a$0$x_1 : UInt<32>
+;CHECK:    node i_1 = i
+;CHECK:    when eqv(i_1, UInt("h0")) :
+;CHECK:       m$0$0$x := a$0$x_1         
+;CHECK:    when eqv(i_1, UInt("h1")) :
+;CHECK:       m$1$0$x := a$0$x_1         
+;CHECK:    a$0$x_1 := b$x_1      
+;CHECK: when eqv(j_1, UInt("h1")) :
+;CHECK:    wire a$1$x_1 : UInt<32>
+;CHECK:    node i_2 = i
+;CHECK:    when eqv(i_2, UInt("h0")) :
+;CHECK:       m$0$1$x := a$1$x_1         
+;CHECK:    when eqv(i_2, UInt("h1")) :
+;CHECK:       m$1$1$x := a$1$x_1         
+;CHECK:    a$1$x_1 := b$x_1      
+;CHECK: b$x_1 := value