diff options
| author | azidar | 2015-02-20 16:56:25 -0800 |
|---|---|---|
| committer | azidar | 2015-02-20 16:56:25 -0800 |
| commit | 95dd261b4e65840ade351dcb00e4164a99daf654 (patch) | |
| tree | 73f5fa894f5ebb3a61581dd2f29ae96e46d476e4 /test/passes/initialize-register | |
| parent | 8299c2ecae1701fa6060185a8aed25543e201eba (diff) | |
Rewrote the initialize-register pass, now correctly implemented
with a new IR construct - Null. LetRec is not implemented, but is
marked with a TODO.
Test cases for this pass are now located in
test/passes/initialize-register
Diffstat (limited to 'test/passes/initialize-register')
| -rw-r--r-- | test/passes/initialize-register/begin.fir | 22 | ||||
| -rw-r--r-- | test/passes/initialize-register/when.fir | 40 |
2 files changed, 62 insertions, 0 deletions
diff --git a/test/passes/initialize-register/begin.fir b/test/passes/initialize-register/begin.fir new file mode 100644 index 00000000..9d4de49e --- /dev/null +++ b/test/passes/initialize-register/begin.fir @@ -0,0 +1,22 @@ +; RUN: firrtl %s abcd | tee %s.out | FileCheck %s + + circuit top : + module top : + input a : UInt(16) + input b : UInt(16) + output z : UInt + + reg r1 : UInt +; CHECK: wire [[R1:gen[0-9]*]] : UInt +; CHECK: n:[[R1]] := Null + + reg r2 : UInt + r2.init := UInt(0) +; CHECK: wire [[R2:gen[0-9]*]] : UInt +; CHECK-NOT: reg:r2 := n:[[R2]] +; CHECK: n:[[R2]] := Null +; CHECK: n:[[R2]] := UInt(0) + +; CHECK: when port:reset : +; CHECK-DAG: reg:r1 := n:[[R1]] +; CHECK-DAG: reg:r2 := n:[[R2]] diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir new file mode 100644 index 00000000..e4749abe --- /dev/null +++ b/test/passes/initialize-register/when.fir @@ -0,0 +1,40 @@ +; RUN: firrtl %s abcd | tee %s.out | FileCheck %s +; CHECK: circuit top : + circuit top : + module top : + input a : UInt(16) + input b : UInt(16) + output z : UInt + when greater(1, 2) : + reg r1: UInt + r1.init := UInt(12) +; CHECK: wire [[R1:gen[0-9]*]] : UInt +; CHECK-NOT: reg:r1 := n:[[R1]] +; CHECK: n:[[R1]] := Null +; CHECK: n:[[R1]] := UInt(12) +; CHECK-NOT: r1.init := UInt(12) + reg r2: UInt +; CHECK: wire [[R2:gen[0-9]*]] : UInt +; CHECK-NOT: reg:r2 := n:[[R2]] +; CHECK: n:[[R2]] := Null + +; CHECK: when port:reset : +; CHECK-DAG: reg:r2 := n:[[R2]] +; CHECK-DAG: reg:r1 := n:[[R1]] + else : + reg r1: UInt + r1.init := UInt(12) +; CHECK: wire [[R1:gen[0-9]*]] : UInt +; CHECK-NOT: reg:r1 := n:[[R1]] +; CHECK: n:[[R1]] := Null +; CHECK: n:[[R1]] := UInt(12) +; CHECK-NOT: r1.init := UInt(12) + + reg r2: UInt +; CHECK: wire [[R2:gen[0-9]*]] : UInt +; CHECK-NOT: reg:r2 := n:[[R2]] +; CHECK: n:[[R2]] := Null + +; CHECK: when port:reset : +; CHECK-DAG: reg:r2 := n:[[R2]] +; CHECK-DAG: reg:r1 := n:[[R1]] |