diff options
| author | jackbackrack | 2015-05-19 16:02:21 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-05-19 16:02:21 -0700 |
| commit | f4edadb530297f4f3e293c81c0d8414f8279b65b (patch) | |
| tree | 643db928ee1a396a2ecbf8477fd3fa6aee9f3927 /test/passes/infer-widths | |
| parent | eb7d0913bd01cffdc2be944c7001721f737b44bf (diff) | |
| parent | 14bb9cda8352388bcd33ba9ca2700805dc51639f (diff) | |
get flo backend running again with no pads and generic operators
Diffstat (limited to 'test/passes/infer-widths')
| -rw-r--r-- | test/passes/infer-widths/dsh.fir | 12 | ||||
| -rw-r--r-- | test/passes/infer-widths/gcd.fir | 8 | ||||
| -rw-r--r-- | test/passes/infer-widths/simple.fir | 4 |
3 files changed, 12 insertions, 12 deletions
diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir index 2cbdfd34..6b683e56 100644 --- a/test/passes/infer-widths/dsh.fir +++ b/test/passes/infer-widths/dsh.fir @@ -1,9 +1,9 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : - module M : + module top : wire x : UInt<16> wire z : SInt<16> wire y : UInt<3> @@ -12,10 +12,10 @@ circuit top : wire c : UInt wire d : SInt - a := dshl-u(x,y) - b := dshl-s(z,y) - c := dshr-u(x,y) - d := dshr-s(z,y) + a := dshl(x,y) + b := dshl(z,y) + c := dshr(x,y) + d := dshr(z,y) ; CHECK: wire a : UInt<23> diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 435540ae..9e4bf0f5 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p ctd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p ctd | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap-uu(x, y) + q := sub-wrap(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,7 +17,7 @@ circuit top : reg y : UInt on-reset x := UInt(0) on-reset y := UInt(42) - when gt-uu(x, y) : + when gt(x, y) : inst s of subtracter s.x := x s.y := y @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := eq-uu(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt<16> diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 0d4dc981..590515e7 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cTwd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cTwd | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : @@ -12,7 +12,7 @@ circuit top : wire c : UInt wire z : UInt - z := mux(c,Pad(a,?),Pad(b,?)) + z := mux(c,a,b) |