diff options
| author | azidar | 2015-04-22 15:24:18 -0700 |
|---|---|---|
| committer | azidar | 2015-04-22 15:24:18 -0700 |
| commit | a4f7aa2b81a021f21a49bd4059d051bc0f949880 (patch) | |
| tree | 3817d244f207bdebaec3e9e4d3601d0ecef546c6 /test/passes/infer-widths | |
| parent | 3b3e1117fa3f346e70d3b8d50b7fd91842fb753b (diff) | |
Switched to stricter primop width constraints. Implemented Pad. Added some missing primops
Diffstat (limited to 'test/passes/infer-widths')
| -rw-r--r-- | test/passes/infer-widths/gcd.fir | 2 | ||||
| -rw-r--r-- | test/passes/infer-widths/simple.fir | 10 |
2 files changed, 10 insertions, 2 deletions
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index a550326b..864852fb 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cT | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cTd | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 432030d5..50eb5452 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cT | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cTwd | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : @@ -6,6 +6,14 @@ circuit top : wire e : UInt(30) reg y : UInt y := e + + wire a : UInt(20) + wire b : UInt(10) + wire c : UInt + wire z : UInt + + z := mux(c,Pad(a,?),Pad(b,?)) + ; CHECK: Finished Infer Widths |